ELECTRICAL BEHAVIOR OF CMOS CIRCUITS

ELECTRICAL BEHAVIOR OF CMOS CIRCUITS

A circuit or system designer must provide in a number of areas adequate engineering design margins - insurance that the circuit will work properly even under the worst of conditions.

The Circuit behavior is studied based on the following:

1.   Logic voltage levels

CMOS devices operating under normal conditions are guaranteed to produce output voltage levels within well-defined LOW and HIGH ranges based on LOW and HIGH input voltage levels over somewhat wider ranges. CMOS manufacturers specify these ranges and operating conditions very carefully to ensure compatibility among different devices in the same family, and to provide a degree of interoperability among devices in different families.

2.   DC noise margins

Nonnegative DC noise margins ensure that the highest LOW voltage produced by an output is always lower than the highest voltage that an input can reliably interpret as LOW, and that the lowest HIGH voltage produced by an output is always higher than the lowest voltage that an input can reliably interpret as HIGH.

3.   Fanout

This refers to the number and type of inputs that are connected to a given output. If too many inputs are connected to an output, the DC noise margins of the circuit may be inadequate. Fanout may also affect the speed at which the output changes from one state to another.

4.   Speed

The time that it takes a CMOS output to change from the LOW state to the HIGH state, or vice versa, depends on both the internal structure of the device and the characteristics of the other devices that it drives, even to the extent of being affected by the wire or printed-circuit-board traces connected to the output. Two separate components of “speed” exist i.e., transition time and propagation delay.

5.   Power consumption

The power consumed by a CMOS device depends on a number of factors, including its internal structure, the input signals that it receives, the other devices that it drives, and how often its output changes between LOW and HIGH.

6.   Noise

The main reason for providing engineering design margins is to ensure proper circuit operation in the presence of noise. Noise can be generated by a number of sources like Cosmic rays, Magnetic fields from nearby machinery, Power-supply disturbances, the switching action of the logic circuits themselves.

7.   Electrostatic discharge

The CMOS device can be damaged just by touching it due to electrostatic discharge.

8.   Open-drain outputs

Some CMOS outputs omit the usual p-channel pullup transistors. In the HIGH state, such outputs are effectively a “no-connection,” which is useful in some applications.

9.   Three-state outputs

Some CMOS devices have an extra “output enable” control input that can be used to disable both the p-channel pull-up transistors and the n-channel pull-down transistors. Many such device outputs can be tied together to create a multisource bus, as long as the control logic is arranged so that at most one output is enabled at a time.