CMOS/TTL Interfacing

CMOS/TTL Interfacing

A digital designer selects a “default” logic family to use in a system, based on general requirements of speed, power, cost, and so on. However, the designer may select devices from other families in some cases because of availability or other special requirements.

There are several factors to consider in TTL/CMOS interfacing

1.   Noise Margin: The LOW-state DC noise margin depends on VOLmax of the driving output and VILmax of the driven input, and equals VILmax - VOLmax. Similarly, the HIGH-state DC noise margin equals VOHmin - VIHmin. Fig.22 shows the relevant numbers for TTL and CMOS families.

Fig.22: Output and input levels for interfacing TTL and CMOS families (HC and VHC inputs are not TTL compatible)

Eg., the LOW-state DC noise margin of HC or HCT driving TTL is 0.8 - 0.33 = 0.47 V, and the HIGH-state is 3.84 - 2.0 =1.84 V. On the other hand, the HIGH-state margin of TTL driving HC or VHC is 2.7 - 3.85 = -1.15 V i.e., TTL driving HC or AC doesn’t work, unless the TTL HIGH output happens to be higher and the CMOS HIGH input threshold happens to be lower by a total of 1.15 V compared to their worst-case specs. To drive CMOS inputs properly from TTL outputs, the CMOS devices should be HCT, VHCT. Or FCT rather than HC or VHC.

2.   Fanout: As with pure TTL, a designer must sum the input current requirements of devices driven by an output and compare with the output’s capabilities in both states. Fanout is not a problem when TTL drives CMOS, since CMOS inputs require almost no current in either state. On the other hand, TTL inputs, especially in the LOW state, require substantial current, especially compared to HC and HCT output capabilities.

Eg., an HC or HCT output can drive 10 LS or only two S-TTL inputs.

3.   Capacitive Loading: The load capacitance increases both the delay and the power dissipation of logic circuits. Increases in delay are especially noticeable with HC and HCT outputs, whose transition times increase about 1 ns for each 5 pF of load capacitance. The transistors in FCT outputs have very low “on” resistances, so their transition times increase only about 0.1 ns for each 5 pF of load capacitance. For a given load capacitance, power-supply voltage, and application, all of the CMOS families have similar dynamic power dissipation, since each variable in the CV²f equation is the same. On the other hand, TTL outputs have somewhat lower dynamic power dissipation, since the voltage swing between TTL HIGH and LOW levels is smaller.

Low-Voltage CMOS Logic and Interfacing

Two important factors have led the IC industry to move towards lower power supply voltages in CMOS devices:

1.   In most applications, CMOS output voltages swing from rail to rail, so the V in the CV²f equation is the power-supply voltage. Cutting power-supply voltage reduces dynamic power dissipation more than proportionally.

2.   As the industry moves towards ever-smaller transistor geometries, the oxide insulation between a CMOS transistor’s gate and its source and drain is getting ever thinner, and thus incapable of insulating voltage potentials as “high” as 5 V.

As a result, JEDEC (Joint Electron Device Engineering Council), an IC industry standards group, selected 3.3V ± 0.3V, 2.5V ± 0.2V, and 1.8V± 0.15V as the next “standard” logic power-supply voltages. JEDEC standards specify the input and output logic voltage levels for devices operating with these power-supply voltages.

Hence 3.3-V CMOS families are allowed to operate with 5-V CMOS and TTL families. Many ASICs and microprocessors have followed a similar approach; these devices are large enough that it can make sense to provide them with two power-supply voltages. A low voltage, such as 2.5 V, is supplied to operate the chip’s internal gates, or core logic. A higher voltage, such as 3.3 V, is supplied to operate the external input and output circuits, or pad ring, for compatibility with older-generation devices in the system. Special buffer circuits are used internally to translate safely and quickly between the core-logic and the pad-ring logic voltages.

3.3-V LVTTL and LVCMOS Logic

The relationships among signal levels for standard TTL and low-voltage CMOS devices operating at their nominal power-supply voltages are illustrated nicely in Fig.23, adapted from a Texas Instruments application note. The original, symmetric signal levels for pure 5-V CMOS families such as HC and VHC are shown in (a). TTL-compatible CMOS families such as HCT, VHCT, and FCT shift the voltage levels downwards for compatibility with TTL as shown in (b).

The first step in the progression of lower CMOS power-supply voltages was 3.3 V. The JEDEC standard for 3.3-V logic actually defines two sets of levels. LVCMOS (low-voltage CMOS) levels are used in pure CMOS applications where outputs have light DC loads (less than 100 mA), so VOL and VOH are maintained within 0.2 V of the power-supply rails. LVTTL (low-voltage TTL) levels, shown in (c), are used in applications where outputs have significant DC loads, so VOL can be as high as 0.4 V and VOH can be as low as 2.4 V.

The positioning of TTL’s logic levels at the low end of the 5-V range was really quite fortuitous. As shown in Fig.23 (b) and (c), it was possible to define the LVTTL levels to match up with TTL levels exactly. Thus, an LVTTL output can drive a TTL input with no problem, as long as its output current specifications (IOLmax, IOHmax) are respectively. Similarly, a TTL output can drive an LVTTL input, except for the problem of driving it beyond LVTTL’s 3.3-V V_CC.

Fig.23: Comparison of Logic levels

5-V Tolerant Inputs

The inputs of a gate won’t necessarily tolerate voltages greater than VCC. This can easily occur when 5-V and 3.3-V logic families in a system. Eg., 5-V CMOS devices easily produce 4.9-V outputs when lightly loaded, and both CMOS and TTL devices routinely produce 4.0-V outputs even when moderately loaded.

The maximum voltage VImax that can be tolerated by an input is listed in the “absolute maximum ratings” section of the manufacturer’s data sheet. For HC devices, VImax equals VCC. Thus, if an HC device is powered by a 3.3-V supply, it cannot be driven by any 5-V CMOS or TTL outputs. For VHC devices, on the other hand, VImax is 7 V; thus, VHC devices with a 3.3-V power supply may be used to convert 5-V outputs to 3.3-V levels for use with 3.3-V microprocessors, memories, and other devices in a pure 3.3-V subsystem.

Fig.24: CMOS input structures (a) non 5-V tolerant HC (b) 5-V tolerant VHC

Fig.24 explains why some inputs are 5-V tolerant and others are not. As shown in (a), the HC and HCT input structure actually contains two reverse biased clamp diodes, between each input signal and VCC and ground.

The purpose of these diodes is specifically to shunt any transient input signal value less than 0 through D1 or greater than VCC through D2 to the corresponding power-supply rail. Such transients can occur as a result of transmission-line reflections. Shunting the “undershoot” or “overshoot” to ground or VCC reduces the magnitude and duration of reflections.

Of course, diode D2 can’t distinguish between transient overshoot and a persistent input voltage greater than VCC. Hence, if a 5-V output is connected to one of these inputs, it will not see the very high impedance normally associated with a CMOS input. Instead, it will see a relatively low impedance path to VCC through the now forward-biased diode D2, and excessive current will flow.

Fig.24 (b) shows a 5-V tolerant CMOS input. This input structure simply omits D2; diode D1 is still provided to clamp undershoots. The VHC and AHC families use this input structure. The kind of input structure shown in Fig.24 (b) is necessary but not sufficient to create 5-V tolerant inputs. The transistors in a device’s particular fabrication process must also be able to withstand voltage potentials higher than VCC. On this basis, VImax in the VHC family is limited to 7.0 V. In many 3.3-V ASIC processes, it’s not possible to get 5-V tolerant inputs, even if you’re willing to give up the transmission-line benefits of diode D2.

5-V Tolerant Outputs

Five-volt tolerance must also be considered for outputs, when both 3.3-V and 5-V three-state outputs are connected to a bus. When the 3.3-V output  is in the disabled, Hi-Z state, a 5-V device may be driving the bus, and a 5-V signal may appear on the 3.3-V device’s output.

Fig.25: CMOS three-state output structures (a) non 5-V tolerant HC and VHC (b) 5-V tolerant LVC

Fig.25 explains why some outputs are 5-V tolerant and others are not. As shown in (a), the standard CMOS three-state output has an n-channel transistor Q1 to ground and a p-channel transistor Q2 to VCC. When the output is disabled, circuitry (not shown) holds the gate of Q1 near 0 V, and the gate of Q2 near VCC, so both transistors are off and Y is Hi-Z.

Consider if VCC is 3.3 V and a different device applies a 5-V signal to the output pin Y in (a). Then the drain of Q2 (Y) is at 5 V while the gate (V2) is still at only 3.3 V. With the gate at a lower potential than the drain, Q2 will begin to conduct and provide a relatively low-impedance path from Y to VCC, and excessive current will flow. Both HC and VHC three-state outputs have this structure and therefore are not 5-V tolerant.

Fig.25 (b) shows a 5-V tolerant output structure. An extra p-channel transistor Q3 is used to prevent Q2 from turning on when it shouldn’t. When VOUT is greater than VCC, Q3 turns on. This forms a relatively low impedance path from Y to the gate of Q2, which now stays off because its gate voltage V2 can no longer be below the drain voltage. This output structure is used in Texas Instruments’ LVC (Low-Voltage CMOS) family.

TTL/LVTTL Interfacing Summary

TTL (5-V) and LVTTL (3.3-V) devices can be mixed in the same system subject to just three rules:

1.    LVTTL outputs can drive TTL inputs directly, subject to the usual constraints on output current (IOLmax, IOHmax) of the driving devices.

2.    TTL outputs can drive LVTTL inputs if the inputs are 5-V tolerant.

3.    TTL and LVTTL three-state outputs can drive the same bus if the LVTTL outputs are 5-V tolerant.

2.5-V and 1.8-V Logic

The transition from 3.3-V to 2.5-V logic will not be so easy. It is true that 3.3-V outputs can drive 2.5-V inputs as long as the inputs are 3.3-V tolerant. However, a quick look at Fig.24(c) and (d) shows that VOH of a 2.5-V output equals VIH of a 3.3-V input. In other words, there is zero HIGH-state DC noise margin when a 2.5-V output drives a 3.3-V input, not a good situation.

Solution: use a level translator or level shifter, a device which is powered by both supply voltages and which internally boosts the lower logic levels (2.5 V) to the higher ones (3.3 V). Many of today’s ASICs and microprocessors contain level translators internally, allowing them to operate with a 2.5-V or 2.7-V core and a 3.3-V pad ring.

The next step will be a transition from 2.5-V to 1.8-V logic as shown in fig.24(d) and (e), you can see that the HIGH-state DC noise margin is actually negative when a 1.8-V output drives a 2.5-V input, so level translators must be used.