CMOS LOGIC FAMILIES

CMOS Logic Families

The first commercially successful CMOS family was 4000-series CMOS.

Advantages: Low Power Dissipation

Disadvantages: fairly slow and were not easy to interface with the most popular logic family of the time, bipolar TTL

Thus, the 4000 series was supplanted in most applications by the more capable CMOS families.

All of the CMOS devices have part numbers of the form “74FAMnn,” where “FAM” is an alphabetic family mnemonic and nn is a numeric function designator. Devices in different families with the same value of nn perform the same function. Eg., the 74HC30, 74HCT30, 74AC30, 74ACT30, and 74AHC30 are all 8-input NAND gates.

The prefix “74” is simply a number that was used by an early, popular supplier of TTL devices, Texas Instruments. The prefix “54” is used for identical parts that are specified for operation over a wider range of temperature and power-supply voltage, for use in military applications. Such parts are usually fabricated in the same way as their 74-series counterparts, except that they are tested, screened, and marked differently, a lot of extra paperwork is generated, and a higher price is charged.

HC and HCT

The first two 74-series CMOS families are HC (High-speed CMOS) and HCT (High-speed CMOS, TTL compatible).

Advantages:

1.   Compared with the original 4000 family, HC and HCT both have higher speed and better current sinking and sourcing capability.

2.   The HCT family uses a power supply voltage VCC of 5 V and can be intermixed with TTL devices, which also use a 5-V supply.

3.   The HC family is optimized for use in systems that use CMOS logic exclusively, and can use any power supply voltage between 2 and 6 V. A higher voltage is used for higher speed, and a lower voltage for lower power dissipation.

Lowering the supply voltage is especially effective, since most CMOS power dissipation is proportional to the square of the voltage (i.e., CV²f power). Even when used with a 5-V supply, HC devices are not quite compatible with TTL. In particular, HC circuits are designed to recognize CMOS input levels.

Assuming a supply voltage of 5.0 V, Fig.39 (a) shows the input and output levels of HC devices. The output levels produced by TTL devices do not quite match this range, so HCT devices use the different input levels shown in fig.39 (b).

These levels are established in the fabrication process by making transistors with different switching thresholds, producing the different transfer characteristics shown in Fig.40. Hence, HC and HCT are essentially identical in their output specifications; only their input levels differ.

VHC and VHCT

Several new CMOS families were introduced in the 1980s and the 1990s. Two of the most recent and probably the most versatile are VHC (Very High-Speed CMOS) and VHCT (Very High-Speed CMOS, TTL compatible). These families are about twice as fast as HC/HCT while maintaining backwards compatibility with their predecessors. Like HC and HCT, the VHC and VHCT families differ from each other only in the input levels that they recognize; their output characteristics are the same.

Also like HC/HCT, VHC/VHCT outputs have symmetric output drive, i.e., an output can sink or source equal amounts of current; the output is just as “strong” in both states. Other logic families, including the FCT and TTL families have asymmetric output drive; they can sink much more current in the LOW state than they can source in the HIGH state.

HC, HCT, VHC, and VHCT Electrical Characteristics

The specifications assume that the devices are used with a nominal 5-V power supply, although (derated) operation is possible with any supply voltage in the range 2–5.5 V (up to 6 V for HC/HCT). Commercial (74-series) parts are intended to be operated at temperatures between 0°C and 70°C, while military (54-series) parts are characterized for operation between -55°C and 125°C.

The specs in Table.3 assume an operating temperature of 25°C. A full manufacturer’s data sheet provides additional specifications for device operation over the entire temperature range.

Most devices within a given logic family have the same electrical specifications for inputs and outputs, typically differing only in power consumption and propagation delay. Table.3 includes specifications for a 74x00 two-input NAND gate and a 74x138 3-to-8 decoder in the HC, HCT, VHC, and VHCT families.

The ’00 NAND gate is included as the smallest logic-design building block in each family, while the ’138 is a “medium-scale” part containing the equivalent of about 15 NAND gates. (The ’138 spec is included to allow comparison with the faster FCT family; ’00 gates are not manufactured in the FCT family.)

The first row specifies propagation delay, two numbers, tpHL and tpLH may be used to specify delay; the number in the table is the worst-case of the two.

From Table.4, HC and HCT are about the same speed as LS TTL, and that VHC and VHCT are almost as fast as ALS TTL. The propagation delay for the ’138 is somewhat longer than for the ’00, since signals must travel through three or four levels of gates internally.

The second and third rows of the table.3 show that the quiescent power dissipation of these CMOS devices is practically nil, well under a milliwatt (mW) if the inputs have CMOS levels—0 V for LOW and VCC for HIGH. (the quiescent power dissipation numbers given for the ’00 are per gate, while for the ’138 they apply to the entire MSI device.)

The dynamic power dissipation of a CMOS gate depends on the voltage swing of the output (usually V_CC), the output transition frequency (f ), and the capacitance that is being charged and discharged on transitions, according to the formula

Here, CPD is the power dissipation capacitance of the device and CL is the capacitance of the load attached to the CMOS output in a given application.

The table lists both CPD and an equivalent dynamic power dissipation factor in units of milliwatts per megahertz, assuming that C_L = 0. Using this factor, the total power dissipation is computed at various frequencies as the sum of the dynamic power dissipation at that frequency and the quiescent power dissipation.

The speed-power product is simply the product of the propagation delay and power consumption of a typical gate; the result is measured in picojoules (pJ). The speed-power product measures a sort of efficiency - how much energy a logic gate uses to switch its output which has to be as low as possible.

Table.5 gives the input specs of typical CMOS devices in each of the families. Some of the specs assume that the 5-V supply has a ±10% margin; i.e., VCC can be anywhere between 4.5 and 5.5 V.

IImax - The maximum input current for any value of input voltage. This spec states that the current flowing into or out of a CMOS input is 1 mA or less for any value of input voltage. In other words, CMOS inputs create almost no DC load on the circuits that drive them.

CINmax - The maximum capacitance of an input. This number can be used when figuring the AC load on an output that drives this and other inputs. Most manufacturers also specify a lower, typical input capacitance of about 5 pF, which gives a good estimate of AC load.

VILmax - The maximum voltage that an input is guaranteed to recognize as LOW. The values are different for HC/VHC versus HCT/VHCT. The “CMOS” value, 1.35 V, is 30% of the minimum power-supply voltage, while the “TTL” value is 0.8 V for compatibility with TTL families.

VIHmin - The minimum voltage that an input is guaranteed to recognize as HIGH.

The “CMOS” value, 3.85 V, is 70% of the maximum power-supply voltage, while the “TTL” value is 2.0 V for compatibility with TTL families. (Unlike CMOS levels, TTL input levels are not symmetric with respect to the power-supply rails.)

The specifications for TTL-compatible CMOS outputs usually have two sets of output parameters; one set or the other is used depending on how an output is loaded. A CMOS load is one that requires the output to sink and source very little DC current, 20 mA for HC/HCT and 50 mA for VHC/VHCT. This is the case when the CMOS outputs drive only CMOS inputs. With CMOS loads, CMOS outputs maintain an output voltage within 0.1 V of the supply rails, 0 and VCC. (A worst-case VCC = 4.5 V is used for the table entries; hence, VOHminC = 4.4 V.)

A TTL load can consume much more sink and source current, up to 4 mA from and HC/HCT output and 8 mA from a VHC/VHCT output. In this case, a higher voltage drop occurs across the “on” transistors in the output circuit, but the output voltage is still guaranteed to be within the normal range of TTL output levels. Table.6 lists CMOS output specifications for both CMOS and TTL loads.

IOLmaxC - The maximum current that an output can supply in the LOW state while driving a CMOS load. Since this is a positive value, current flows into the output pin.

IOLmaxT - The maximum current that an output can supply in the LOW state while driving a TTL load.

VOLmaxC - The maximum voltage that a LOW output is guaranteed to produce while driving a CMOS load, i.e., as long as IOLmaxC is not exceeded.

VOLmaxT - The maximum voltage that a LOW output is guaranteed to produce while driving a TTL load, i.e., as long as IOLmaxT is not exceeded.

IOHmaxC - The maximum current that an output can supply in the HIGH state while driving a CMOS load. Since this is a negative value, positive current flows out of the output pin.

IOHmaxT - The maximum current that an output can supply in the HIGH state while driving a TTL load.

VOHminC - The minimum voltage that a HIGH output is guaranteed to produce while driving a CMOS load, i.e., as long as IOHmaxC is not exceeded.

VOHminT - The minimum voltage that a HIGH output is guaranteed to produce while driving a TTL load, i.e., as long as IOHmaxT is not exceeded.

The voltage parameters above determine DC noise margins. The LOW state

DC noise margin is the difference between VOLmax and VILmax. This depends on the characteristics of both the driving output and the driven inputs.

Eg., the LOW-state DC noise margin of a HCT driving a few HCT inputs (a CMOS load) is 0.8 - 0.1 = 0.7 V. With a TTL load, the noise margin for the HCT inputs drops to 0.8 - 0.33 = 0.47 V. Similarly, the HIGH-state DC noise margin is the difference between VOHmin and VIHmin.

In general, when different families are interconnected, we have to compare the appropriate VOLmax and VOHmin of the driving gate with VILmax and VIHmin of all the driven gates to determine the worst-case noise margins.

The IOLmax and IOHmax parameters in the table determine fanout capability, and are especially important when an output drives inputs in one or more different families.

Two calculations must be performed to determine whether an output is operating within its rated fanout capability:

HIGH-state fanout - The IIHmax values for all of the driven inputs are added. The sum must be less than IOHmax of the driving output.

LOW-state fanout - The IILmax values for all of the driven inputs are added. The sum must be less than IOLmax of the driving output.

FCT and FCT-T

In the early 1990s, another CMOS family FCT was launched. The key benefit of the FCT (Fast CMOS, TTL compatible) family was its ability to meet or exceed the speed and the output drive capability of the best TTL families while reducing power consumption and maintaining full compatibility with TTL.

The original FCT family had the drawback of producing a full 5-V CMOS VOH, creating enormous CV²f power dissipation and circuit noise as its outputs swung from 0 V to almost 5 V in high-speed (25 MHz+) applications.

A variation of the family, FCT-T (Fast CMOS, TTL compatible with TTL VOH), was quickly introduced with circuit innovations to reduce the HIGH-level output voltage, thereby reducing both power consumption and switching noise while maintaining the same high operating speed as the original FCT.

A suffix of “T” is used on part numbers to denote the FCT-T output structure, for example, 74FCT138T versus 74FCT138. The FCT-T family remains very popular today. A key application of FCT-T is driving buses and other heavy loads. Compared with other CMOS families, it can source or sink gobs of current, up to 64 mA in the LOW state.

FCT-T Electrical Characteristics

Electrical characteristics of the 5-V FCT-T family are summarized in Table.7. The family is specifically designed to be intermixed with TTL devices, so its operation is only specified with a nominal 5-V supply and TTL logic levels. Some manufacturers are beginning to sell parts with similar capabilities using a 3.3-V supply, and using the FCT designation. However, they are different devices with different part numbers.

Individual logic gates are not manufactured in the FCT family. The simplest FCT logic element is a 74FCT138T decoder, which has six inputs, eight outputs, and contains the equivalent of about a dozen 4-input gates internally. Comparing its propagation delay and power consumption in Table.7 with the corresponding HCT and VHCT numbers in Table.3, the FCT-T family is superior in both speed and power dissipation. When comparing, note that FCT-T manufacturers specify only maximum, not typical propagation delays.

Unlike other CMOS families, FCT-T does not have a CPD specification. Instead, it has an ICCD specification, where I_CCD - Dynamic power supply current, in units of mA/MHz which is the amount of additional power supply current that flows when one input is changing at the rate of 1 MHz. The ICCD specification gives the same information as CPD, but in a different way.

The circuit’s internal power dissipation due to transitions at a given frequency f can be calculated by the formula

Thus, ICCD/VCC is algebraically equivalent to the CPD specification of other CMOS families. FCT-T also has a DICC specification for the extra quiescent current that is consumed with nonideal HIGH inputs.