CMOS STEADY-STATE ELECTRICAL BEHAVIOR

CMOS STEADY-STATE ELECTRICAL BEHAVIOR

The steady-state behavior is the circuits’ behavior when inputs and outputs are not changing.

1. Logic Levels and Noise Margins

The complete input-output transfer characteristic of a CMOS Inverter is shown in fig.20, where the input voltage is varied from 0 to 5 V, as shown on the X axis; the Y axis plots the output voltage. If we define a CMOS LOW input level as any voltage under 2.4 V, and a HIGH input level as anything over 2.6 V, then only when the input is between 2.4 and 2.6 V does the inverter produce a nonlogic output voltage under this definition.

Unfortunately, the typical transfer characteristic shown in Fig.20 is not guaranteed. It varies greatly under different conditions of power supply voltage, temperature, and output loading. The transfer characteristic may even vary depending on when the device was fabricated.

Sound engineering practice dictates that we use more conservative specifications for LOW and HIGH. The conservative specs for a typical CMOS logic family (HC-series) are shown in Fig.21. These parameters are specified by CMOS device manufacturers in data sheets.

V_OHmin - The minimum output voltage in the HIGH state.

V_IHmin - The minimum input voltage guaranteed to be recognized as a HIGH.

V_ILmax - The maximum input voltage guaranteed to be recognized as a LOW.

V_OLmax - The maximum output voltage in the LOW state.

The input voltages are determined mainly by switching thresholds of the two

transistors, while the output voltages are determined mainly by the “on” resistance of the transistors.

All of the parameters in Figure 3-26 are guaranteed by CMOS manufacturers over a range of temperature and output loading. Parameters are also guaranteed over a range of power-supply voltage VCC, typically 5.0 V±10%.

When the device outputs are connected only to other CMOS inputs, the output current is low (eg., IOL ≤ 20 mA), there is very little voltage drop across the output transistors.

The power-supply voltage VCC and ground are often called the power supply

rails. CMOS levels are typically a function of the power-supply rails:

VOHmin VCC - 0.1 V

VIHmin 70% of VCC

VILmax 30% of VCC

VOLmax ground + 0.1 V

From table.1, VOHmin is specified as 4.4 V which is only a 0.1-V drop from VCC, since the worst-case number is specified with VCC at its minimum value of 5.0-10% = 4.5 V.

DC noise margin is a measure of how much noise it takes to corrupt a worst-case output voltage into a value that may not be recognized properly by an input. For HC-series CMOS in the LOW state, VILmax (1.35 V) exceeds VOLmax (0.1 V) by 1.25 V so the LOW-state DC noise margin is 1.25 V. Likewise, there is DC noise margin of 1.25 V in the HIGH state. In general, CMOS outputs have excellent DC noise margins when driving other CMOS inputs.

Regardless of the voltage applied to the input of a CMOS inverter, the input

consumes very little current, only the leakage current of the two transistors’

gates. The maximum amount of current that can flow is also specified by the

device manufacturer as

IIH - The maximum current that flows into the input in the LOW state.

IIL - The maximum current that flows into the input in the HIGH state.

The input current shown in Table.1 for the ’HC00 is only ±1 mA, i.e., it takes very little power to maintain a CMOS input in one state or the other. This is in sharp contrast to bipolar logic circuits like TTL and ECL, whose inputs may consume significant current (and power) in one or both states.

CIRCUIT BEHAVIOR WITH RESISTIVE LOADS

CMOS gate inputs have very high impedance and consume very little current from the circuits that drive them. There are other devices which require nontrivial amounts of current to operate. When such a device is connected to a CMOS output, called as resistive load or a DC load.

Examples of resistive loads:

1.   Discrete resistors may be included to provide transmission-line termination.

2.   Discrete resistors may not really be present in the circuit, but the load presented by one or more TTL or other non-CMOS inputs may be modeled by a simple resistor network.

3.   The resistors may be part of or may model a current-consuming device such as a light-emitting diode (LED) or a relay coil.

When the output of a CMOS circuit is connected to a resistive load, the output behavior is not nearly as ideal. In either logic state, the CMOS output transistor that is “on” has a nonzero resistance, and a load connected to the output terminal will cause a voltage drop across this resistance. Hence in the LOW state, the output voltage may be somewhat higher than 0.1 V, and in the HIGH state it may be lower than 4.4 V.

Fig.22(a) shows the resistive model. The p-channel and n-channel transistors have resistances Rp and Rn, respectively. In normal operation, one resistance is high (> 1 MW) and the other is low (perhaps 100 W), depending on whether the input voltage is HIGH or LOW. The load in this circuit consists of two resistors attached to the supply rails; a real circuit may have any resistor values, or an even more complex resistive network. In any case, a resistive load, consisting only of resistors and voltage sources, can always be modeled by a Thévenin equivalent network as shown in Fig.22(b).

The Thévenin voltage of the resistive load, including its connection to VCC, is established by the 1kΩ and 2kΩ resistors, which form a voltage divider:

  

The short-circuit current, I_SC = 5V)/1kΩ = 5 mA, so the Thévenin resistance, R_Th = 3.33V/5mA = 667Ω which is the parallel equivalent resistance of the 1kΩ and 2kΩ resistors.

When the CMOS inverter has a HIGH input, the output should be LOW; the actual output voltage can be predicted using the resistive model as shown in Fig.23. The p-channel transistor is “off” and has a very high resistance, high enough to be negligible in the calculations that follow.

The n-channel transistor is “on” and has a low resistance, which we assume to be 100Ω. (The actual “on” resistance depends on the CMOS family and other characteristics such as operating temperature). The “on” transistor and the Thévenin-equivalent resistor R_Thev in Fig.23 form a simple voltage divider.  The resulting output voltage can be calculated as

Similarly, when the inverter has a LOW input, the output should be HIGH and the actual output voltage can be predicted with the model in Fig.24. Assume the p-channel transistor’s “on” resistance is 200Ω. Once again, the “on” transistor and the Thévenin-equivalent resistor R_Thev in the figure form a simple voltage divider, and the resulting output voltage can be calculated as

 IC manufacturers usually don’t specify the equivalent resistances of the “on” transistors, so as we don’t have the necessary information to make the calculation anyway. Instead, IC manufacturers specify a maximum load for the output in each state (HIGH or LOW), and guarantee a worst-case output voltage for that load. The load is specified in terms of current:

IOLmax - The maximum current that the output can sink in the LOW state while still maintaining an output voltage no greater than VOLmax.

IOHmax - The maximum current that the output can source in the HIGH state while still maintaining an output voltage no less than VOHmin.

These definitions are shown in Fig.25. A device output is said to sink current when current flows from the power supply, through the load, and through the device output to ground as in fig.25(a). The output is said to source current when current flows from the power supply, out of the device output, and through the load to ground as in fig.25(b).

Most CMOS devices have two sets of loading specifications. One set is for “CMOS loads,” where the device output is connected to other CMOS inputs, which consume very little current. The other set is for “TTL loads,” where the output is connected to resistive loads such as TTL inputs or other devices that consume significant current. For example, the specifications for HC-series CMOS outputs were shown in Table.1 and are repeated in Table.2. The output current in the HIGH state is shown as a negative number. By convention, the current flow measured at a device terminal is positive if positive current flows into the device; in the HIGH state, current flows out of the output terminal.

As the table shows, with CMOS loads, the CMOS gate’s output voltage is maintained within 0.1 V of the power-supply rail. With TTL loads, the output voltage may degrade quite a bit. Also for the same output current (±4 mA) the maximum voltage drop with respect to the power-supply rail is twice as much in the HIGH state (0.66 V) as in the LOW state (0.33 V). These suggest that the p-channel transistors in HC-series CMOS have a higher “on” resistance than that of the n-channel transistors. Also in any CMOS circuit, a p-channel transistor has over twice the “on” resistance of an n-channel transistor with the same area. Equal voltage drops in both states could be obtained by making the p-channel transistors much larger than the n-channel transistors.

Ohm’s law can be used to determine how much current an output sources or sinks in a given situation. In Fig.23, the “on” n-channel transistor modeled by a 100Ω resistor has a 0.43-V drop across it; therefore it sinks (0.43V)/(100Ω) = 4.3 mA of current. Similarly, the “on” p-channel transistor in Fig.24 sources (0.39V)/(200Ω) = 1.95 mA.

The actual “on” resistances of CMOS output transistors usually aren’t published, so it’s not always possible to use the exact models. However, we can estimate “on” resistances using the following equations, which rely on specifications that are always published

 

These equations use Ohm’s law to compute the “on” resistance as the voltage drop across the “on” transistor divided by the current through it with a worst case resistive load.

Using the numbers given for HC-series CMOS in Table.2, we can calculate Rp(on) = 175 W and Rn(on) = 82.5 W. Very good worst-case estimates of output current can be made by assuming that there is no voltage drop across the “on” transistor. This assumption simplifies the analysis, and yields a conservative result that is almost always good enough for practical purposes.

For Eg., consider Fig.26 which shows a CMOS inverter driving the same Thévenin equivalent load. Assume that there is no voltage drop across the “on” CMOS transistor. In (a), with the output LOW, the entire 3.33-V Thévenin equivalent voltage source appears across R_Thev, and the estimated sink current is (3.33V)/(667Ω) = 5mA. In (b), with the output HIGH and assuming a 5V supply, the voltage drop across R_Thev is 1.67 V, and the estimated source current is (1.67V)/(667Ω) = 2.5mA.

An important feature of the CMOS inverter is that the output structure by itself consumes very little current in either state, HIGH or LOW. In either state, one of the transistors is in the high-impedance “off” state. All of the current flow occurs when a resistive load is connected to the CMOS output. If there’s no load, then there’s no current flow, and the power consumption is zero. With a load, the current flows through both the load and the “on” transistor, and power is consumed in both.

CIRCUIT BEHAVIOR WITH NONIDEAL INPUTS

The behavior of a real CMOS inverter circuit depends on the input voltage as well as on the characteristics of the load. If the input voltage is not close to the power-supply rail, then the “on” transistor may not be fully “on” and its resistance may increase. Likewise, the “off” transistor may not be fully “off’ and its resistance may be quite a bit less than one mega ohm. These two effects combine to move the output voltage away from the power-supply rail.

For eg., consider a CMOS inverter’s possible behavior with a 1.5-V input as shown in Fig.27. Assume the p-channel transistor’s resistance has doubled at this point, and that the n-channel transistor is beginning to turn on. In the figure, the output at 4.31 V is still well within the valid range for a HIGH signal, but not quite the ideal of 5.0 V. Similarly, with a 3.5-V input in (b), the LOW output is 0.24 V, not 0 V. The slight degradation of output voltage is generally tolerable; what’s worse is that the output structure is now consuming a nontrivial amount of power.

The current flow with the 1.5-V input is

and the power consumption is 

The output voltage of a CMOS inverter deteriorates further with a resistive load. Fig.28 shows a CMOS inverter’s possible behavior with a resistive load. With a 1.5-V input, the output at 3.98 V is still within the valid range for a HIGH signal, but it is far from the ideal of 5.0 V. Similarly, with a 3.5-V input as shown in Fig.29, the LOW output is 0.93 V, not 0 V.

In “pure” CMOS systems, all of the logic devices in a circuit are CMOS. Since CMOS inputs have a very high impedance, they present very little resistive load to the CMOS outputs that drive them. Therefore, the CMOS output levels all remain very close to the power-supply rails (0 V and 5 V), and none of the devices waste power in their output structures. On the other hand, if TTL outputs or other nonideal logic signals are connected to CMOS inputs, then the CMOS outputs use power. In addition, if TTL inputs or other resistive loads are connected to CMOS outputs, then the CMOS outputs use power.

FANOUT

The fanout of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specifications. The fanout depends not only on the characteristics of the output, but also on the inputs that it is driving. Fanout must be examined for both possible output states, HIGH and LOW.

For eg., consider Table.2, the maximum LOW-state output current IOLmaxC for an HC-series CMOS gate driving CMOS inputs is 0.02 mA (20 mA). The maximum input current IImax for an HC-series CMOS input in any state is ±1 mA. Therefore, the LOW-state fanout for an HC-series output driving HC-series inputs is 20.

Also the maximum HIGH-state output current IOHmaxC is -0.02mA (-20µA). Hence the HIGH-state fanout for an HC-series output driving HC-series inputs is also 20 i.e., The HIGH-state and LOW-state fanouts of a gate are not necessarily equal. In general, the overall fanout of a gate is the minimum of its HIGH state and LOW-state fanouts, i.e., 20. Assume that we need to maintain the gate’s output at CMOS levels, i.e., within 0.1 V of the power supply rails. If we were willing to live with somewhat degraded, TTL output

levels, then we could use IOLmaxT and IOHmaxT in the fanout calculation. According to Table.2, these specifications are 4.0 mA and -4.0 mA, respectively. Therefore, the fanout of an HC-series output driving HC-series inputs at TTL levels is 4000, virtually unlimited, apparently.

These calculations give the DC fanout, defined as the number of inputs that an output can drive with the output in a constant state (HIGH or LOW). Even if the DC fanout specification is met, a CMOS output driving a large number of inputs may not behave satisfactorily on transitions, LOW-to-HIGH or vice versa.

During transitions, the CMOS output must charge or discharge the stray capacitance associated with the inputs that it drives. If this capacitance is too large, the transition from LOW to HIGH (or vice versa) may be too slow, causing improper system operation. The ability of an output to charge and discharge stray capacitance is sometimes called AC fanout, though it is seldom calculated as precisely as DC fanout.

EFFECTS OF LOADING

Loading an output beyond its rated fanout has several effects:

1.   In the LOW state, the output voltage (VOL) may increase beyond VOLmax.

2.   In the HIGH state, the output voltage (VOH) may fall below VOHmin.

3.   Propagation delay to the output may increase beyond specifications.

4.   Output rise and fall times may increase beyond their specifications.

5.   The operating temperature of the device may increase, thereby reducing the reliability of the device and eventually causing device failure.

The first four effects reduce the DC noise margins and timing margins of the circuit. Thus, a slightly overloaded circuit may work properly in ideal conditions, but experience says that it will fail once it’s out of the friendly environment of the engineering lab.

UNUSED INPUTS

In a real design, sometimes all of the inputs of a logic gate are not used i.e., we may need an n-input gate but have only an n+1-input gate available.

1.   Tying together two inputs of the n+1-input gate gives it the functionality of an n-input gate. Fig.30(a) shows a NAND gate with its inputs tied together.

2.   We can also tie unused inputs to a constant logic value. An unused AND or NAND input should be tied to logic 1, as in (b),

3.   An unused OR or NOR input should be tied to logic 0, as in (c).

In high-speed circuit design, it’s usually better to use method (b) or (c) rather than (a), which increases the capacitive load on the driving signal and may slow things down. In (b) and (c), a resistor value in the range 1–10 kΩ is typically used, and a single pull-up or pull-down resistor can serve multiple unused inputs. It is also possible to tie unused inputs directly to the appropriate power-supply rail.

Unused CMOS inputs should never be left unconnected (or floating. On one hand, such an input will behave as if it had a LOW signal applied to it and will normally show a value of 0 V when probed with an oscilloscope or voltmeter. Hence an unused OR or NOR input can be left floating, because it will act as if a logic 0 is applied and not affect the gate’s output. However, since CMOS inputs have such high impedance, it takes only a small amount of circuit noise to temporarily make a floating input look HIGH, creating some very nasty intermittent circuit failures.

CURRENT SPIKES AND DECOUPLING CAPACITORS

When a CMOS output switches between LOW and HIGH, current flows from VCC to ground through the partially-on p- and n-channel transistors. These currents, often called current spikes because of their brief duration, may show up as noise on the power-supply and ground connections in a CMOS circuit, especially when multiple outputs are switched simultaneously.

For this reason, systems that use CMOS circuits require decoupling capacitors between VCC and ground. These capacitors must be distributed throughout the circuit, at least one within an inch or so of each chip, to supply current during transitions. The large filtering capacitors typically found in the power supply itself don’t satisfy this requirement, because stray wiring inductance prevents them from supplying the current fast enough, hence the need for a physically distributed system of decoupling capacitors.

HOW TO DESTROY A CMOS DEVICE

Hit it with a sledge hammer. Or simply walk across a carpet and then touch an input pin with your finger. Because CMOS device inputs have such high impedance, they are subject to damage from electrostatic discharge (ESD). ESD occurs when a buildup of charge on one surface arcs through a dielectric to another surface with the opposite charge. In the case of a CMOS input, the dielectric is the insulation between an input transistor’s gate and its source and drain. ESD may damage this insulation, causing a short circuit between the device’s input and output.

The input structures of modern CMOS devices use various measures to reduce their susceptibility to ESD damage, but no device is completely immune. Therefore, to protect CMOS devices from ESD damage during shipment and handling, manufacturers normally package their devices in conductive bags, tubes, or foam. To prevent ESD damage when handling loose CMOS devices, circuit assemblers and technicians usually wear conductive wrist straps that are connected by a coil cord to earth ground; this prevents a static charge from building up on their bodies as they move around the factory or lab.

Once a CMOS device is installed in a system, another possible source of damage is latch-up. The physical input structure of just about any CMOS device contains parasitic bipolar transistors between VCC and ground configured as a silicon-controlled rectifier (SCR).” In normal operation, this “parasitic SCR” has no effect on device operation. However, an input voltage that is less than ground or more than VCC can “trigger” the SCR, creating a virtual short-circuit between VCC and ground. Once the SCR is triggered, the only way to turn it off is to turn off the power supply. Before you have a chance to do this, enough power may be dissipated to destroy the device (i.e., we may see smoke).

One possible trigger for latch-up is “undershoot” on high-speed HIGH-to- LOW signal transitions. In this situation, the input signal may go several volts below ground for several nanoseconds before settling into the normal LOW range. However, modern CMOS logic circuits are fabricated with special structures that prevent latch-up in this transient case.

Latch-up can also occur when CMOS inputs are driven by the outputs of another system or subsystem with a separate power supply. If a HIGH input is applied to a CMOS gate before power is present, the gate may come up in the “latched-up” state when power is applied.

Also, modern CMOS logic circuits are fabricated with special structures that prevent latch-up in most cases. However, if the driving output is capable of sourcing lots of current (e.g., tens of mA), latchup is still possible. One solution to this problem is to apply power before hooking up input cables.

ELIMINATE RUDE, SHOCKING BEHAVIOR!

Some design engineers consider themselves above such inconveniences, but to be safe we should follow several ESD precautions in the lab:

1.   Before handling a CMOS device, touch the grounded metal case of a pluggedin instrument or another source of earth ground.

2.   Before transporting a CMOS device, insert it in conductive foam.

3.   When carrying a circuit board containing CMOS devices, handle the board by the edges, and touch a ground terminal on the board to earth ground before poking around with it.

4.   When handing over a CMOS device to a partner, especially on a dry winter day, touch the partner first.