Comparison of Logic Families

Comparison of digital logic families

Family	Basic Gate	Fanout	Pd (mW/Gate)	Noise Immunity	Propagation Delay (nS/Gate)	Cock (MHz)
TTL	NAND	10	10	VG	10	35
TTL-H	NAND	10	22	VG	6	50
TTL-L	NAND	20	1	VG	33	3
TTL-LS	NAND	20	2	VG	9.5	45
TTL-S	NAND	10	19	VG	3	125
TTL-AS	NAND	40	10	VG	1.4	175
TTL-ALS	NAND	20	1	VG	4	50
ECL 10K	OR-NOR	25	40-55	P	2	>60
ECL 100K	OR-NOR	25	40-55	P	0.75	600
MOS	NAND	20	0.2-10	G	300	2
74C	NOR/NAND	50	0.01/1	VG	70	10
74HC	NOR/NAND	20	0.0025/0.6	VG	18	60
74HCT	NOR/NAND	20	0.0025/0.6	VG	18	60
74AC	NOR/NAND	50	0.005/0.75	VG	5.25	100
74ACT	NOR/NAND	50	0.005/0.75	VG	4.75	100

Figures of merit can be calculated as product of propagation delay and power dissipation Pd

For CMOS, Pd is static/dynamic (1MHz) and figure of merit is calculated for each.

TotalPd=staticPd + DynamicPd

VG=VeryGood G=Good P=Poor

Comparison of Logic Families

Parameter	TTL	CMOS	ECL
Propagation Delay	10nS	70nS	750pS
Noise Margin	0.4V	0.45VDD	150mV
Power Dissipation	10mW	0.01mW	5mW
Fanout	10	50	25
Figure of Merit	100pJ	0.7pJ	0.5pJ

Hence from Table,

ECL is the Fastest Logic Family.

CMOS is the Low Power Dissipating Family.