DESIGN FLOW

DESIGN FLOW

Fig.1: Design Flow

Steps in the design flow:

1.   Hierarchical / block diagram. Figuring out the basic approach and building blocks at the block-diagram level. Large logic designs are usually hierarchical, and VHDL gives you a good framework for defining modules and their interfaces and filling in the details later.

2.   Coding. Actual writing of VHDL code for modules, their interfaces, and their internal details.

3.   Compilation. Analyses your code for syntax errors and checks it for compatibility with other modules on which it relies. Compilation also creates the internal information that is needed for simulation.

4.   Simulation. A VHDL simulator allows you to define and apply inputs to your design, and to observe its outputs. Simulation is part of a larger step called verification. A functional verification is performed to verify that the circuit’s logical operation works as desired independent of timing considerations and gate delays.

5.   Synthesis. Converting the VHDL description into a set of primitives or components that can be assembled in the target technology. For example, with PLDs or CPLDs, the synthesis tool may generate two-level sum-of-products equations. With ASICs, it may generate a netlist that specifies how the gates should be interconnected.

6.   Fitting / Placement & Routing. Maps the synthesized components onto physical devices.

7.   Timing verification. At this stage, the actual circuit delays due to wire lengths, electrical loading, and other factors are known, so precise timing simulation can be performed. Study the circuit’s operation including estimated delays, and we verify that the setup, hold, and other timing requirements for sequential devices like flip-flops are met.