CMOS Dynamic Electrical Behavior

CMOS DYNAMIC ELECTRICAL BEHAVIOR

Both the speed and the power consumption of a CMOS device depend to a large extent on AC or dynamic characteristics of the device and its load, that is, what happens when the output changes between states. As part of the internal design of CMOS ASICs, logic designers must carefully examine the effects of output loading and redesign where the load is too high. Even in board-level design, the effects of loading must be considered for clocks, buses, and other signals that have high fanout or long interconnections.

Speed depends on two characteristics, transition time and propagation delay.

TRANSITION TIME

The amount of time that the output of a logic circuit takes to change from one state to another is called the transition time. Fig.31(a) shows how we might like outputs to change state—in zero time. However, real outputs cannot change instantaneously, because they need time to charge the stray capacitance of the wires and other components that they drive. A more realistic view of a circuit’s output is shown in (b). An output takes a certain time, called the rise time (tr), to change from LOW to HIGH, and a possibly different time, called the fall time (tf), to change from HIGH to LOW.

 Even Fig.31(b) is not quite accurate, because the rate of change of the output voltage does not change instantaneously, either. Instead, the beginning and the end of a transition are smooth, as shown in (c). To avoid difficulties in defining the endpoints, rise and fall times are normally measured at the boundaries of the valid logic levels as indicated in the figure. With the convention in (c), the rise and fall times indicate how long an output voltage takes to pass through the “undefined” region between LOW and HIGH. The initial part of a transition is not included in the rise- or fall-time number. Instead, the initial part of a transition contributes to the “propagation delay” number.

The rise and fall times of a CMOS output depends mainly on two factors, the “on” transistor resistance and the load capacitance.

A large capacitance increases transition times; since this is undesirable, it is very rare for a logic designer to purposely connect a capacitor to a logic circuit’s output. However, stray capacitance (a capacitive load or an AC Load) is present in every circuit; it comes from at least three sources:

1.   Output circuits, including a gate’s output transistors, internal wiring, and packaging, have some capacitance associated with them, on the order of 2-10 picofarads (pF) in typical logic families, including CMOS.

2.   The wiring that connects an output to other inputs has capacitance, about 1 pF per inch or more, depending on the wiring technology.

3.   Input circuits, including transistors, internal wiring, and packaging, have capacitance, from 2 to 15 pF per input in typical logic families.

A CMOS output’s rise and fall times can be analyzed using the equivalent circuit shown in Fig.32. The p-channel and n-channel transistors are modeled by resistances Rp and Rn, respectively. In normal operation, one resistance is high and the other is low, depending on the output’s state.

 The output’s load is modeled by an equivalent load circuit with three components:

RL, VL These two components represent the DC load and determine the voltages and currents that are present when the output has settled into a stable HIGH or LOW state. The DC load doesn’t have too much effect on transition times when the output changes states.

CL This capacitance represents the AC load and determines the voltages and currents that are present while the output is changing, and how long it takes to change from one state to the other. When a CMOS output drives only CMOS inputs, the DC load is negligible. To simplify matters, we’ll analyze only this case, with RL = ∞ and VL = 0, in the remainder of this subsection. The presence of a non-negligible DC load would affect the results, but not dramatically.

For the purposes of this analysis of the transition times of a CMOS output, Assume CL= 100 pF, a moderate capacitive load and the “on” resistances of the p-channel and n-channel transistors are 200Ω and 100Ω, respectively.

The rise and fall times depend on how long it takes to charge or discharge the capacitive load CL.

The electrical conditions in the circuit when the output is in a steady HIGH state as shown in Fig.33(a). (RL and VL are not drawn; they have no effect, since we assume R_L = ∞.) Assume that when CMOS transistors change between “on” and “off,” they do so instantaneously. Assume at time t = 0 the CMOS output changes to the LOW state, resulting in the situation as shown in (b).

At time t = 0, V_OUT is still 5.0 V. (A useful electrical engineering maxim is that the voltage across a capacitor cannot change instantaneously.) At time t = ∞, the capacitor must be fully discharged and V_OUT will be 0 V. In between, the value of V_OUT is governed by an exponential law:

The factor R_nC_L has units of seconds, and is called an RC time constant. The preceding calculation shows that the RC time constant for HIGH-to-LOW transitions is 10 nanoseconds (ns).

 Fig.34 shows VOUT as a function of time. To calculate fall time, consider 1.5 V and 3.5 V are the defined boundaries for LOW and HIGH levels for CMOS inputs being driven by the CMOS output. To obtain the fall time, solve the preceding equation for V_OUT = 3.5 and V_OUT =1.5, yielding:

The fall time t_f is the difference between these two numbers, or about 8.5 ns.

For calculation of Rise time, consider Fig.35(a) that shows the conditions in the circuit when the output is in a steady LOW state. If at time t = 0 the CMOS output changes to the HIGH state, the situation depicted in (b) results. Once again, V_OUT cannot change instantly, but at time t = ∞, the capacitor will be fully charged and V_OUT will be 5V.

The value of V_OUT in between is governed by an exponential law:

  

The RC time constant in this case is 20 ns. Fig.36 plots V_OUT as a function of time. To obtain the rise time, solve the preceding equation for V_OUT = 1.5 and V_OUT = 3.5, yielding

 The rise time tr is the difference between these two numbers, or about 17 ns. Assume the p-channel transistor has twice the resistance of the n-channel one, and as a result the rise time is twice as long as the fall time. It takes longer for the “weak” p-channel transistor to pull the output up than it does for the “strong” n-channel transistor to pull it down; the output’s drive capability is “asymmetric.” High-speed CMOS devices are sometimes fabricated with larger p-channel transistors to make the transition times more nearly equal and output drive more symmetric.

Regardless of the transistors’ characteristics, an increase in the load capacitance cause an increase in the RC time constant, and a corresponding increase in the transition times of the output. Thus, it is a goal of high-speed circuit designers to minimize load capacitance, especially on the most timing-critical signals, i.e., by minimizing the number of inputs driven by the signal, by creating multiple copies of the signal, and by careful physical layout of the circuit.

Practically for digital circuits, the transition times are estimated, without going through a detailed analysis. A useful rule of thumb is that the transition time approximately equals the RC time constant of the charging or discharging circuit.

Manufacturers of commercial CMOS circuits typically do not specify transistor “on” resistances on their data sheets, but the same information published in the manufacturers’ application notes.

An “on” resistance can be estimated as the voltage drop across the “on” transistor divided by the current through it with a worst-case resistive load by using

Propagation Delay

Rise and fall times only partially describe the dynamic behavior of a logic element; we need additional parameters to relate output timing to input timing.

A signal path is the electrical path from a particular input signal to a particular output signal of a logic element.

The propagation delay tp of a signal path is the amount of time that it takes for a change in the input signal to produce a change in the output signal.

A complex logic element with multiple inputs and outputs may specify a different value of tp for each different signal path. Also, different values may be specified for a particular signal path, depending on the direction of the output change.

Ignoring rise and fall times, Fig.37(a) shows two different propagation delays for the input-to-output signal path of a CMOS inverter, depending on the direction of the output change:

tpHL - The time between an input change and the corresponding output change when the output is changing from HIGH to LOW.

tpLH - The time between an input change and the corresponding output change when the output is changing from LOW to HIGH.

There are several factors which lead to nonzero propagation delays like

·         In a CMOS device, the rate at which transistors change state is influenced both by the semiconductor physics of the device and by the circuit environment, including input-signal transition rate, input capacitance, and output loading.

·         Multistage devices such as noninverting gates or more complex logic functions may require several internal transistors to change state before the output can change state.

·         Even when the output begins to change state, with nonzero rise and fall times it takes quite some time to cross the region between states.

All of these factors are included in propagation delay.

To factor out the effect of rise and fall times, manufacturers usually specify

propagation delays at the midpoints of input and output transitions, as shown in Fig.37(b). However, sometimes the delays are specified at the logic-level boundary points, especially if the device’s operation may be adversely affected by slow rise and fall times.

Eg., Fig.38 shows how the minimum input pulse width for an SR latch might be specified. In addition, a manufacturer may specify absolute maximum input rise and fall times that must be satisfied to guarantee proper operation. High-speed CMOS circuits may consume excessive current or oscillate if their input transitions are too slow.

Power Consumption

The power consumption of a CMOS circuit whose output is not changing is

called static power dissipation or quiescent power dissipation. Most CMOS circuits have very low static power dissipation, hence they are attractive for laptop computers and other low-power applications—when computation pauses, very little power is consumed. A CMOS circuit consumes significant power only during transitions; this is called dynamic power dissipation.

One source of dynamic power dissipation is the partial short-circuiting of the CMOS output structure. When the input voltage is not close to one of the power supply rails (0V or V_CC), both the p-channel and n-channel output transistors may be partially “on,” creating a series resistance of 600Ω or less. In this case, current flows through the transistors from V_CC to ground. The amount of power consumed in this way depends on both the value of V_CC and the rate at which output transitions occur, according to the formula

 Where

P_T - The circuit’s internal power dissipation due to output transitions.

V_CC - The power supply voltage. As all electrical engineers know, power dissipation across a resistive load (the partially-on transistors) is proportional to the square of the voltage.

f - The transition frequency of the output signal, specifies the number of power-consuming output transitions per second. (frequency is defined as the number of transitions divided by 2.)

C_PD - The power dissipation capacitance is a constant, normally specified by the device manufacturer, completes the formula. CPD turns out to have units of capacitance, but does not represent an actual output capacitance.

Rather, it embodies the dynamics of current flow through the changing output-transistor resistances during a single pair of output transitions, HIGH-to-LOW and LOW-to-HIGH.

Eg., C_PD for HC-series CMOS gates is typically 20–24 pF, even though the actual output capacitance is much less.

The P_T formula is valid only if input transitions are fast enough, leading to fast output transitions. If the input transitions are too slow, then the output transistors stay partially on for a longer time, and power consumption increases. Device manufacturers usually recommend a maximum input rise and fall time, below which the value specified for CPD is valid.

Another more significant source of CMOS power consumption is the capacitive load (C_L) on the output. During a LOW-to-HIGH transition, current flows through a p-channel transistor to charge CL. Likewise, during a HIGH-to-LOW transition, current flows through an n-channel transistor to discharge C_L. In each case, power is dissipated in the “on” resistance of the transistor. The P_L is used to denote the total amount of power dissipated by charging and discharging C_L. The units of PL are power, or energy usage per unit time. The energy for one transition could be determined by calculating the current through the charging transistor as a function of time, squaring this function, multiplying by the “on” resistance of the charging transistor, and integrating over time.

During a transition, the voltage across the load capacitance C_L changes by ±V_CC. According to the definition of capacitance, the total amount of charge that must flow to make a voltage change of V_CC across C_L is C_L * V_CC. The total amount of energy used in one transition is charge times the average voltage change. The first little bit of charge makes a voltage change of V_CC, while the last bit of charge makes a vanishingly small voltage change, hence the average change is V_CC/2. The total energy per transition is therefore C_L*V_CC²/2. If there are 2f transitions per second, the total power dissipated due to the capacitive load is

  The total dynamic power dissipation of a CMOS circuit is the sum of PT and PL:

Based on this formula, dynamic power dissipation is often called CV²f power. In most applications of CMOS circuits, CV²f power is the major contributor to total power dissipation. CV²f power is also consumed by bipolar logic circuits like TTL and ECL, but at low to moderate frequencies it is insignificant compared to the static (DC or quiescent) power dissipation of bipolar circuits.