Emitter Coupled Logic

Emitter-Coupled Logic

The key to reducing propagation delay in a bipolar logic family is to prevent a gate’s transistors from saturating. Schottky diodes prevent saturation in TTL gates. However, it is also possible to prevent saturation by using a radically different circuit structure, called current-mode logic (CML) or emitter-coupled logic (ECL).

Unlike the other logic families, CML does not produce a large voltage swing between the LOW and HIGH levels. Instead, it has a small voltage swing, less than a volt, and it internally switches current between two possible paths, depending on the output state.

The first CML logic family was introduced by General Electric in 1961. The concept was soon refined by Motorola and others to produce the still popular 10K and 100K emitter-coupled logic (ECL) families.

Advantages: These families are extremely fast i.e, offer propagation delays as short as 1 ns. The newest ECL family, ECLinPS (literally, ECL in picoseconds), offers maximum delays under 0.5 ns (500 ps), including the signal delay getting on and off of the IC package.

Throughout the evolution of digital circuit technology, some type of ECL has always been the fastest technology for discrete, packaged logic components.

Disadvantages:

1.   More Power Consumption hence not popular. In fact, high power consumption made the design of ECL supercomputers, such as the Cray-1 and Cray-2, as much of a challenge in cooling technology as in digital design.

2.   ECL has a poor speed-power product

3.   ECL does not provide a high level of integration

4.   ECL has fast edge rates requiring design for transmission-line effects in most applications

5.   ECL is not directly compatible with TTL and CMOS.

Applications:

ECL still finds its place as a logic and interface technology in very high-speed communications gear, including fiber-optic transceiver interfaces for gigabit Ethernet and Asynchronous Transfer Mode (ATM) networks.

Basic CML Circuit

The basic idea of current-mode logic is illustrated by the inverter/buffer circuit in Fig.26. This circuit has both an inverting output (OUT1) and a noninverting output (OUT2). Two transistors are connected as a differential amplifier with a common emitter resistor. The supply voltages for this example are VCC = 5.0, VBB = 4.0, and VEE = 0 V, and the input LOW and HIGH levels are defined to be 3.6 and 4.4 V. This circuit actually produces output LOW and HIGH levels that are 0.6 V higher (4.2 and 5.0 V), but this is corrected in real ECL circuits.

Fig.26: Basic CML inverter/buffer circuit with input HIGH

When VIN is HIGH, transistor Q1 is on, but not saturated, and transistor Q2 is OFF, true due to careful choice of resistor values and voltage levels. Thus, VOUT2 is pulled to 5.0 V (HIGH) through R2, and it can be shown that the voltage drop across R1 is about 0.8 V so that VOUT1 is about 4.2 V (LOW). Also V_E = V_OUT1 - V_Q1 = 4.2V - 0.4V = 3.8V as Q1 is completely turned ON.

Fig.27: Basic CML inverter/buffer Circuit with Input Low

When VIN is LOW, as shown in Fig.27, transistor Q2 is on, but not saturated, and transistor Q1 is OFF. Thus, VOUT1 is pulled to 5.0 V through R1, and it can be shown that VOUT2 is about 4.2 V. Also V_E = V_OUT2 - V_Q2 = 4.2V - 0.8V = 3.4V as Q1 is nearly turned ON.

The outputs of this inverter are called differential outputs as they are always complementary, and it is possible to determine the output state by looking at the difference between the output voltages (VOUT1 - VOUT2) rather than their absolute values. i.e., the output is 1 if (VOUT1 - VOUT2) > 0, and it is 0 if (VOUT1 - VOUT2) > 0. It is possible to build input circuits with two wires per logical input that define the logical signal value; these are called differential inputs.

Differential signals are used in most ECL “interfacing” and “clock distribution” applications because of their low skew and high noise immunity. They are “low skew” because the timing of a 0-to-1 or 1-to-0 transition does not depend critically on voltage thresholds, which may change with temperature or between devices. Instead, the timing depends only on when the voltages cross over relative to each other.

The “relative” definition of 0 and 1 provides outstanding noise immunity, since noise created by variations in the power supply or coupled from external sources tend to be common-mode signals that affect both differential signals similarly, leaving the difference value unchanged.

It is also possible to determine the logic value by sensing the absolute voltage level of one input signal, called a single-ended input. Single ended signals are used in most ECL “logic” applications to avoid the obvious expense of doubling the number of signal lines. The basic CML inverter in Fig.27 has a single-ended input. It always has both “outputs” available internally; the circuit is actually either an inverter or a non-inverting buffer depending on whether we use OUT1 or OUT2. To perform logic with the basic circuit of Fig.27, we simply place additional transistors in parallel with Q1, similar to the approach in a TTL NOR gate.

Fig.28 shows a 2-input CML OR/NOR gate, if any input is HIGH, the corresponding input transistor is active, and VOUT1 is LOW (NOR output). At the same time, Q3 is OFF, and VOUT2 is HIGH (OR output).

The input levels for the inverter/buffer are defined to be 3.6 and 4.4 V, while the output levels that it produces are 4.2 and 5.0 V which is a problem.

Remedy:  put a diode in series with each output to lower it by 0.6 V to match the input levels, but that still leaves another problem—the outputs have poor fanout.

A HIGH output must supply base current to the inputs that it drives, and this current creates an additional voltage drop across R1 or R2, reducing the output voltage.

Remedy: Use ECL 10K/10H Families

Fig.28: CML 2-input OR/NOR Gate (a) Circuit Diagram (b) Function Table

(c) Logic Symbol (d) Truth Table

ECL 10K/10H Families

The packaged components in today’s most popular ECL family have 5-digit part numbers of the form “10xxx” (e.g., 10102, 10181, 10209), so the family is generically called ECL 10K.

The improvements over the basic CML circuit are

1.   An emitter-follower output stage shifts the output levels to match the input levels and provides very high current-driving capability, up to 50 mA per output. It is also responsible for the family’s name, “emitter-coupled” logic.

2.   An internal bias network provides VBB without the need for a separate, external power supply.

3.   The family is designed to operate with VCC = 0 (ground) and VEE = -5.2 V. In most applications, ground signals are more noise-free than the power supply signals. In ECL, the logic signals are referenced to the algebraically higher power-supply voltage rail, so the family’s designers decided to make that 0 V (the “clean” ground) and use a negative voltage for VEE. The power-supply noise that does appear on VEE is a common-mod” signal that is rejected by the input structure’s differential amplifier.

4.   Parts with a 10H prefix (the ECL 10H family) are fully voltage compensated, so they work properly with power-supply voltages other than VEE = -5.2 V.

Logic LOW and HIGH levels are defined in the ECL 10K family as shown in Fig.29. Note that even though the power supply is negative, ECL assigns the names LOW and HIGH to the algebraically lower and higher voltages, respectively.

Fig.29: ECL 10K Logic Levels

DC noise margins in ECL 10K are much less than in CMOS and TTL, only 0.155 V in the LOW state and 0.125 V in the HIGH state. However, ECL gates do not need as much noise margin as these families. Unlike CMOS and TTL, an ECL gate generates very little power-supply and ground noise when it changes state; its current requirement remains constant as it merely steers current from one path to another. Also, ECL’s emitter-follower outputs have very low impedance in either state, and it is difficult to couple noise from an external source into a signal line driven by such a low-impedance output.

Fig.30(a) is the circuit for an ECL OR/NOR gate, one section of a quad OR/NOR gate with part number 10102. A pull-down resistor on each input ensures that if the input is left unconnected, it is treated as LOW. The bias network has component values selected to generate V_BB = -1.29 V for proper operation of the differential amplifier. Each output transistor, using the emitter follower configuration, maintains its emitter voltage at one diode-drop below its base voltage, thereby achieving the required output level shift. Fig.30(b) summarizes the electrical operation of the gate.

When V_X = V_Y = -1.8V, then Q1 and Q2 are turned OFF and Q3 is Turned ON which allows V_C3 (-1.2V) < V_C2 (-0.2V). Hence V_E = V_C3 - V_Q3. Let V_C3 ≈ V_BB = -1.29V, then V_E= -1.29V -0.6V = -1.89V ≈ -1.9V. Also V_OUT1 = V_C2 - V_Q5 = -0.2V -0.7V = -0.9V and V_OUT2 = V_C3 - V_Q6 = -1.2V -0.6V = -1.8V.

When V_X = V_Y = -0.9V, then Q1 and Q2 are turned ON and Q3 is Turned OFF which allows V_C3 (-1.2V) > V_C2 (-0.2V). Hence V_E = V_C2 - V_Q1 = -1.2V -0.3V = -1.5V. Also V_OUT2 = V_C2-V_Q5 = -0.2V -0.7V = -0.9V and V_OUT1 = V_C3 - V_Q6 = -1.2V -0.6V = -1.8V.

The emitter-follower outputs used in ECL 10K require external pull-down resistors. The 10K family is designed to use external rather than internal pull-down resistors for good reason. The rise and fall times of ECL output transitions are so fast (typically 2 ns) that any connection longer than a few inches must be treated as a transmission line, and must be terminated.

Fig.30: Two-input 10K ECL OR/NOR gate (a) Circuit Diagram (b) Function Table (c) Truth Table (d) Logic Symbol

Rather than waste power with an internal pull down resistor, ECL 10K allows the designer to select an external resistor that satisfies both pull-down and transmission-line termination requirements. The simplest termination, sufficient for short connections, is to connect a resistor in the range of 270 W to 2 kW from each output to VEE.

A typical ECL 10K gate has a propagation delay of 2ns, comparable to 74AS TTL. With its outputs left unconnected, a 10K gate consumes about 26mW of power, also comparable to a 74AS TTL gate, which consumes about 20mW. However, the termination required by ECL 10K also consumes power, from 10 to 150mW per output depending on the termination circuit configuration.

A 74AS TTL output may or may not require a power-consuming termination circuit, depending on the physical characteristics of the application.

ECL 100K Families

Members of the ECL 100K family have 6-digit part numbers of the form “100xxx” (e.g., 100101, 100117, 100170), but in general have functions different than 10K parts with similar numbers. The 100K family has the following major differences from the 10K family:

• Reduced power-supply voltage, VEE = -4.5 V.

• Different logic levels, as a consequence of the different supply voltage.

• Shorter propagation delays, typically 0.75 ns.

• Shorter transition times, typically 0.70 ns.

• Higher power consumption, typically 40 mW per gate.