CMOS Dynamic Electrical Behavior

CMOS DYNAMIC ELECTRICAL BEHAVIOR

Both the speed and the power consumption of a CMOS device depend to a large extent on AC or dynamic characteristics of the device and its load, that is, what happens when the output changes between states. As part of the internal design of CMOS ASICs, logic designers must carefully examine the effects of output loading and redesign where the load is too high. Even in board-level design, the effects of loading must be considered for clocks, buses, and other signals that have high fanout or long interconnections.

Speed depends on two characteristics, transition time and propagation delay.

TRANSITION TIME

The amount of time that the output of a logic circuit takes to change from one state to another is called the transition time. Fig.31(a) shows how we might like outputs to change state—in zero time. However, real outputs cannot change instantaneously, because they need time to charge the stray capacitance of the wires and other components that they drive. A more realistic view of a circuit’s output is shown in (b). An output takes a certain time, called the rise time (tr), to change from LOW to HIGH, and a possibly different time, called the fall time (tf), to change from HIGH to LOW.

 Even Fig.31(b) is not quite accurate, because the rate of change of the output voltage does not change instantaneously, either. Instead, the beginning and the end of a transition are smooth, as shown in (c). To avoid difficulties in defining the endpoints, rise and fall times are normally measured at the boundaries of the valid logic levels as indicated in the figure. With the convention in (c), the rise and fall times indicate how long an output voltage takes to pass through the “undefined” region between LOW and HIGH. The initial part of a transition is not included in the rise- or fall-time number. Instead, the initial part of a transition contributes to the “propagation delay” number.

The rise and fall times of a CMOS output depends mainly on two factors, the “on” transistor resistance and the load capacitance.

A large capacitance increases transition times; since this is undesirable, it is very rare for a logic designer to purposely connect a capacitor to a logic circuit’s output. However, stray capacitance (a capacitive load or an AC Load) is present in every circuit; it comes from at least three sources:

1.   Output circuits, including a gate’s output transistors, internal wiring, and packaging, have some capacitance associated with them, on the order of 2-10 picofarads (pF) in typical logic families, including CMOS.

2.   The wiring that connects an output to other inputs has capacitance, about 1 pF per inch or more, depending on the wiring technology.

3.   Input circuits, including transistors, internal wiring, and packaging, have capacitance, from 2 to 15 pF per input in typical logic families.

A CMOS output’s rise and fall times can be analyzed using the equivalent circuit shown in Fig.32. The p-channel and n-channel transistors are modeled by resistances Rp and Rn, respectively. In normal operation, one resistance is high and the other is low, depending on the output’s state.

 The output’s load is modeled by an equivalent load circuit with three components:

RL, VL These two components represent the DC load and determine the voltages and currents that are present when the output has settled into a stable HIGH or LOW state. The DC load doesn’t have too much effect on transition times when the output changes states.

CL This capacitance represents the AC load and determines the voltages and currents that are present while the output is changing, and how long it takes to change from one state to the other. When a CMOS output drives only CMOS inputs, the DC load is negligible. To simplify matters, we’ll analyze only this case, with RL = ∞ and VL = 0, in the remainder of this subsection. The presence of a non-negligible DC load would affect the results, but not dramatically.

For the purposes of this analysis of the transition times of a CMOS output, Assume CL= 100 pF, a moderate capacitive load and the “on” resistances of the p-channel and n-channel transistors are 200Ω and 100Ω, respectively.

The rise and fall times depend on how long it takes to charge or discharge the capacitive load CL.

The electrical conditions in the circuit when the output is in a steady HIGH state as shown in Fig.33(a). (RL and VL are not drawn; they have no effect, since we assume R_L = ∞.) Assume that when CMOS transistors change between “on” and “off,” they do so instantaneously. Assume at time t = 0 the CMOS output changes to the LOW state, resulting in the situation as shown in (b).

At time t = 0, V_OUT is still 5.0 V. (A useful electrical engineering maxim is that the voltage across a capacitor cannot change instantaneously.) At time t = ∞, the capacitor must be fully discharged and V_OUT will be 0 V. In between, the value of V_OUT is governed by an exponential law:

The factor R_nC_L has units of seconds, and is called an RC time constant. The preceding calculation shows that the RC time constant for HIGH-to-LOW transitions is 10 nanoseconds (ns).

 Fig.34 shows VOUT as a function of time. To calculate fall time, consider 1.5 V and 3.5 V are the defined boundaries for LOW and HIGH levels for CMOS inputs being driven by the CMOS output. To obtain the fall time, solve the preceding equation for V_OUT = 3.5 and V_OUT =1.5, yielding:

The fall time t_f is the difference between these two numbers, or about 8.5 ns.

For calculation of Rise time, consider Fig.35(a) that shows the conditions in the circuit when the output is in a steady LOW state. If at time t = 0 the CMOS output changes to the HIGH state, the situation depicted in (b) results. Once again, V_OUT cannot change instantly, but at time t = ∞, the capacitor will be fully charged and V_OUT will be 5V.

The value of V_OUT in between is governed by an exponential law:

  

The RC time constant in this case is 20 ns. Fig.36 plots V_OUT as a function of time. To obtain the rise time, solve the preceding equation for V_OUT = 1.5 and V_OUT = 3.5, yielding

 The rise time tr is the difference between these two numbers, or about 17 ns. Assume the p-channel transistor has twice the resistance of the n-channel one, and as a result the rise time is twice as long as the fall time. It takes longer for the “weak” p-channel transistor to pull the output up than it does for the “strong” n-channel transistor to pull it down; the output’s drive capability is “asymmetric.” High-speed CMOS devices are sometimes fabricated with larger p-channel transistors to make the transition times more nearly equal and output drive more symmetric.

Regardless of the transistors’ characteristics, an increase in the load capacitance cause an increase in the RC time constant, and a corresponding increase in the transition times of the output. Thus, it is a goal of high-speed circuit designers to minimize load capacitance, especially on the most timing-critical signals, i.e., by minimizing the number of inputs driven by the signal, by creating multiple copies of the signal, and by careful physical layout of the circuit.

Practically for digital circuits, the transition times are estimated, without going through a detailed analysis. A useful rule of thumb is that the transition time approximately equals the RC time constant of the charging or discharging circuit.

Manufacturers of commercial CMOS circuits typically do not specify transistor “on” resistances on their data sheets, but the same information published in the manufacturers’ application notes.

An “on” resistance can be estimated as the voltage drop across the “on” transistor divided by the current through it with a worst-case resistive load by using

Propagation Delay

Rise and fall times only partially describe the dynamic behavior of a logic element; we need additional parameters to relate output timing to input timing.

A signal path is the electrical path from a particular input signal to a particular output signal of a logic element.

The propagation delay tp of a signal path is the amount of time that it takes for a change in the input signal to produce a change in the output signal.

A complex logic element with multiple inputs and outputs may specify a different value of tp for each different signal path. Also, different values may be specified for a particular signal path, depending on the direction of the output change.

Ignoring rise and fall times, Fig.37(a) shows two different propagation delays for the input-to-output signal path of a CMOS inverter, depending on the direction of the output change:

tpHL - The time between an input change and the corresponding output change when the output is changing from HIGH to LOW.

tpLH - The time between an input change and the corresponding output change when the output is changing from LOW to HIGH.

There are several factors which lead to nonzero propagation delays like

·         In a CMOS device, the rate at which transistors change state is influenced both by the semiconductor physics of the device and by the circuit environment, including input-signal transition rate, input capacitance, and output loading.

·         Multistage devices such as noninverting gates or more complex logic functions may require several internal transistors to change state before the output can change state.

·         Even when the output begins to change state, with nonzero rise and fall times it takes quite some time to cross the region between states.

All of these factors are included in propagation delay.

To factor out the effect of rise and fall times, manufacturers usually specify

propagation delays at the midpoints of input and output transitions, as shown in Fig.37(b). However, sometimes the delays are specified at the logic-level boundary points, especially if the device’s operation may be adversely affected by slow rise and fall times.

Eg., Fig.38 shows how the minimum input pulse width for an SR latch might be specified. In addition, a manufacturer may specify absolute maximum input rise and fall times that must be satisfied to guarantee proper operation. High-speed CMOS circuits may consume excessive current or oscillate if their input transitions are too slow.

Power Consumption

The power consumption of a CMOS circuit whose output is not changing is

called static power dissipation or quiescent power dissipation. Most CMOS circuits have very low static power dissipation, hence they are attractive for laptop computers and other low-power applications—when computation pauses, very little power is consumed. A CMOS circuit consumes significant power only during transitions; this is called dynamic power dissipation.

One source of dynamic power dissipation is the partial short-circuiting of the CMOS output structure. When the input voltage is not close to one of the power supply rails (0V or V_CC), both the p-channel and n-channel output transistors may be partially “on,” creating a series resistance of 600Ω or less. In this case, current flows through the transistors from V_CC to ground. The amount of power consumed in this way depends on both the value of V_CC and the rate at which output transitions occur, according to the formula

 Where

P_T - The circuit’s internal power dissipation due to output transitions.

V_CC - The power supply voltage. As all electrical engineers know, power dissipation across a resistive load (the partially-on transistors) is proportional to the square of the voltage.

f - The transition frequency of the output signal, specifies the number of power-consuming output transitions per second. (frequency is defined as the number of transitions divided by 2.)

C_PD - The power dissipation capacitance is a constant, normally specified by the device manufacturer, completes the formula. CPD turns out to have units of capacitance, but does not represent an actual output capacitance.

Rather, it embodies the dynamics of current flow through the changing output-transistor resistances during a single pair of output transitions, HIGH-to-LOW and LOW-to-HIGH.

Eg., C_PD for HC-series CMOS gates is typically 20–24 pF, even though the actual output capacitance is much less.

The P_T formula is valid only if input transitions are fast enough, leading to fast output transitions. If the input transitions are too slow, then the output transistors stay partially on for a longer time, and power consumption increases. Device manufacturers usually recommend a maximum input rise and fall time, below which the value specified for CPD is valid.

Another more significant source of CMOS power consumption is the capacitive load (C_L) on the output. During a LOW-to-HIGH transition, current flows through a p-channel transistor to charge CL. Likewise, during a HIGH-to-LOW transition, current flows through an n-channel transistor to discharge C_L. In each case, power is dissipated in the “on” resistance of the transistor. The P_L is used to denote the total amount of power dissipated by charging and discharging C_L. The units of PL are power, or energy usage per unit time. The energy for one transition could be determined by calculating the current through the charging transistor as a function of time, squaring this function, multiplying by the “on” resistance of the charging transistor, and integrating over time.

During a transition, the voltage across the load capacitance C_L changes by ±V_CC. According to the definition of capacitance, the total amount of charge that must flow to make a voltage change of V_CC across C_L is C_L * V_CC. The total amount of energy used in one transition is charge times the average voltage change. The first little bit of charge makes a voltage change of V_CC, while the last bit of charge makes a vanishingly small voltage change, hence the average change is V_CC/2. The total energy per transition is therefore C_L*V_CC²/2. If there are 2f transitions per second, the total power dissipated due to the capacitive load is

  The total dynamic power dissipation of a CMOS circuit is the sum of PT and PL:

Based on this formula, dynamic power dissipation is often called CV²f power. In most applications of CMOS circuits, CV²f power is the major contributor to total power dissipation. CV²f power is also consumed by bipolar logic circuits like TTL and ECL, but at low to moderate frequencies it is insignificant compared to the static (DC or quiescent) power dissipation of bipolar circuits.

CMOS LOGIC FAMILIES

CMOS Logic Families

The first commercially successful CMOS family was 4000-series CMOS.

Advantages: Low Power Dissipation

Disadvantages: fairly slow and were not easy to interface with the most popular logic family of the time, bipolar TTL

Thus, the 4000 series was supplanted in most applications by the more capable CMOS families.

All of the CMOS devices have part numbers of the form “74FAMnn,” where “FAM” is an alphabetic family mnemonic and nn is a numeric function designator. Devices in different families with the same value of nn perform the same function. Eg., the 74HC30, 74HCT30, 74AC30, 74ACT30, and 74AHC30 are all 8-input NAND gates.

The prefix “74” is simply a number that was used by an early, popular supplier of TTL devices, Texas Instruments. The prefix “54” is used for identical parts that are specified for operation over a wider range of temperature and power-supply voltage, for use in military applications. Such parts are usually fabricated in the same way as their 74-series counterparts, except that they are tested, screened, and marked differently, a lot of extra paperwork is generated, and a higher price is charged.

HC and HCT

The first two 74-series CMOS families are HC (High-speed CMOS) and HCT (High-speed CMOS, TTL compatible).

Advantages:

1.   Compared with the original 4000 family, HC and HCT both have higher speed and better current sinking and sourcing capability.

2.   The HCT family uses a power supply voltage VCC of 5 V and can be intermixed with TTL devices, which also use a 5-V supply.

3.   The HC family is optimized for use in systems that use CMOS logic exclusively, and can use any power supply voltage between 2 and 6 V. A higher voltage is used for higher speed, and a lower voltage for lower power dissipation.

Lowering the supply voltage is especially effective, since most CMOS power dissipation is proportional to the square of the voltage (i.e., CV²f power). Even when used with a 5-V supply, HC devices are not quite compatible with TTL. In particular, HC circuits are designed to recognize CMOS input levels.

Assuming a supply voltage of 5.0 V, Fig.39 (a) shows the input and output levels of HC devices. The output levels produced by TTL devices do not quite match this range, so HCT devices use the different input levels shown in fig.39 (b).

These levels are established in the fabrication process by making transistors with different switching thresholds, producing the different transfer characteristics shown in Fig.40. Hence, HC and HCT are essentially identical in their output specifications; only their input levels differ.

VHC and VHCT

Several new CMOS families were introduced in the 1980s and the 1990s. Two of the most recent and probably the most versatile are VHC (Very High-Speed CMOS) and VHCT (Very High-Speed CMOS, TTL compatible). These families are about twice as fast as HC/HCT while maintaining backwards compatibility with their predecessors. Like HC and HCT, the VHC and VHCT families differ from each other only in the input levels that they recognize; their output characteristics are the same.

Also like HC/HCT, VHC/VHCT outputs have symmetric output drive, i.e., an output can sink or source equal amounts of current; the output is just as “strong” in both states. Other logic families, including the FCT and TTL families have asymmetric output drive; they can sink much more current in the LOW state than they can source in the HIGH state.

HC, HCT, VHC, and VHCT Electrical Characteristics

The specifications assume that the devices are used with a nominal 5-V power supply, although (derated) operation is possible with any supply voltage in the range 2–5.5 V (up to 6 V for HC/HCT). Commercial (74-series) parts are intended to be operated at temperatures between 0°C and 70°C, while military (54-series) parts are characterized for operation between -55°C and 125°C.

The specs in Table.3 assume an operating temperature of 25°C. A full manufacturer’s data sheet provides additional specifications for device operation over the entire temperature range.

Most devices within a given logic family have the same electrical specifications for inputs and outputs, typically differing only in power consumption and propagation delay. Table.3 includes specifications for a 74x00 two-input NAND gate and a 74x138 3-to-8 decoder in the HC, HCT, VHC, and VHCT families.

The ’00 NAND gate is included as the smallest logic-design building block in each family, while the ’138 is a “medium-scale” part containing the equivalent of about 15 NAND gates. (The ’138 spec is included to allow comparison with the faster FCT family; ’00 gates are not manufactured in the FCT family.)

The first row specifies propagation delay, two numbers, tpHL and tpLH may be used to specify delay; the number in the table is the worst-case of the two.

From Table.4, HC and HCT are about the same speed as LS TTL, and that VHC and VHCT are almost as fast as ALS TTL. The propagation delay for the ’138 is somewhat longer than for the ’00, since signals must travel through three or four levels of gates internally.

The second and third rows of the table.3 show that the quiescent power dissipation of these CMOS devices is practically nil, well under a milliwatt (mW) if the inputs have CMOS levels—0 V for LOW and VCC for HIGH. (the quiescent power dissipation numbers given for the ’00 are per gate, while for the ’138 they apply to the entire MSI device.)

The dynamic power dissipation of a CMOS gate depends on the voltage swing of the output (usually V_CC), the output transition frequency (f ), and the capacitance that is being charged and discharged on transitions, according to the formula

Here, CPD is the power dissipation capacitance of the device and CL is the capacitance of the load attached to the CMOS output in a given application.

The table lists both CPD and an equivalent dynamic power dissipation factor in units of milliwatts per megahertz, assuming that C_L = 0. Using this factor, the total power dissipation is computed at various frequencies as the sum of the dynamic power dissipation at that frequency and the quiescent power dissipation.

The speed-power product is simply the product of the propagation delay and power consumption of a typical gate; the result is measured in picojoules (pJ). The speed-power product measures a sort of efficiency - how much energy a logic gate uses to switch its output which has to be as low as possible.

Table.5 gives the input specs of typical CMOS devices in each of the families. Some of the specs assume that the 5-V supply has a ±10% margin; i.e., VCC can be anywhere between 4.5 and 5.5 V.

IImax - The maximum input current for any value of input voltage. This spec states that the current flowing into or out of a CMOS input is 1 mA or less for any value of input voltage. In other words, CMOS inputs create almost no DC load on the circuits that drive them.

CINmax - The maximum capacitance of an input. This number can be used when figuring the AC load on an output that drives this and other inputs. Most manufacturers also specify a lower, typical input capacitance of about 5 pF, which gives a good estimate of AC load.

VILmax - The maximum voltage that an input is guaranteed to recognize as LOW. The values are different for HC/VHC versus HCT/VHCT. The “CMOS” value, 1.35 V, is 30% of the minimum power-supply voltage, while the “TTL” value is 0.8 V for compatibility with TTL families.

VIHmin - The minimum voltage that an input is guaranteed to recognize as HIGH.

The “CMOS” value, 3.85 V, is 70% of the maximum power-supply voltage, while the “TTL” value is 2.0 V for compatibility with TTL families. (Unlike CMOS levels, TTL input levels are not symmetric with respect to the power-supply rails.)

The specifications for TTL-compatible CMOS outputs usually have two sets of output parameters; one set or the other is used depending on how an output is loaded. A CMOS load is one that requires the output to sink and source very little DC current, 20 mA for HC/HCT and 50 mA for VHC/VHCT. This is the case when the CMOS outputs drive only CMOS inputs. With CMOS loads, CMOS outputs maintain an output voltage within 0.1 V of the supply rails, 0 and VCC. (A worst-case VCC = 4.5 V is used for the table entries; hence, VOHminC = 4.4 V.)

A TTL load can consume much more sink and source current, up to 4 mA from and HC/HCT output and 8 mA from a VHC/VHCT output. In this case, a higher voltage drop occurs across the “on” transistors in the output circuit, but the output voltage is still guaranteed to be within the normal range of TTL output levels. Table.6 lists CMOS output specifications for both CMOS and TTL loads.

IOLmaxC - The maximum current that an output can supply in the LOW state while driving a CMOS load. Since this is a positive value, current flows into the output pin.

IOLmaxT - The maximum current that an output can supply in the LOW state while driving a TTL load.

VOLmaxC - The maximum voltage that a LOW output is guaranteed to produce while driving a CMOS load, i.e., as long as IOLmaxC is not exceeded.

VOLmaxT - The maximum voltage that a LOW output is guaranteed to produce while driving a TTL load, i.e., as long as IOLmaxT is not exceeded.

IOHmaxC - The maximum current that an output can supply in the HIGH state while driving a CMOS load. Since this is a negative value, positive current flows out of the output pin.

IOHmaxT - The maximum current that an output can supply in the HIGH state while driving a TTL load.

VOHminC - The minimum voltage that a HIGH output is guaranteed to produce while driving a CMOS load, i.e., as long as IOHmaxC is not exceeded.

VOHminT - The minimum voltage that a HIGH output is guaranteed to produce while driving a TTL load, i.e., as long as IOHmaxT is not exceeded.

The voltage parameters above determine DC noise margins. The LOW state

DC noise margin is the difference between VOLmax and VILmax. This depends on the characteristics of both the driving output and the driven inputs.

Eg., the LOW-state DC noise margin of a HCT driving a few HCT inputs (a CMOS load) is 0.8 - 0.1 = 0.7 V. With a TTL load, the noise margin for the HCT inputs drops to 0.8 - 0.33 = 0.47 V. Similarly, the HIGH-state DC noise margin is the difference between VOHmin and VIHmin.

In general, when different families are interconnected, we have to compare the appropriate VOLmax and VOHmin of the driving gate with VILmax and VIHmin of all the driven gates to determine the worst-case noise margins.

The IOLmax and IOHmax parameters in the table determine fanout capability, and are especially important when an output drives inputs in one or more different families.

Two calculations must be performed to determine whether an output is operating within its rated fanout capability:

HIGH-state fanout - The IIHmax values for all of the driven inputs are added. The sum must be less than IOHmax of the driving output.

LOW-state fanout - The IILmax values for all of the driven inputs are added. The sum must be less than IOLmax of the driving output.

FCT and FCT-T

In the early 1990s, another CMOS family FCT was launched. The key benefit of the FCT (Fast CMOS, TTL compatible) family was its ability to meet or exceed the speed and the output drive capability of the best TTL families while reducing power consumption and maintaining full compatibility with TTL.

The original FCT family had the drawback of producing a full 5-V CMOS VOH, creating enormous CV²f power dissipation and circuit noise as its outputs swung from 0 V to almost 5 V in high-speed (25 MHz+) applications.

A variation of the family, FCT-T (Fast CMOS, TTL compatible with TTL VOH), was quickly introduced with circuit innovations to reduce the HIGH-level output voltage, thereby reducing both power consumption and switching noise while maintaining the same high operating speed as the original FCT.

A suffix of “T” is used on part numbers to denote the FCT-T output structure, for example, 74FCT138T versus 74FCT138. The FCT-T family remains very popular today. A key application of FCT-T is driving buses and other heavy loads. Compared with other CMOS families, it can source or sink gobs of current, up to 64 mA in the LOW state.

FCT-T Electrical Characteristics

Electrical characteristics of the 5-V FCT-T family are summarized in Table.7. The family is specifically designed to be intermixed with TTL devices, so its operation is only specified with a nominal 5-V supply and TTL logic levels. Some manufacturers are beginning to sell parts with similar capabilities using a 3.3-V supply, and using the FCT designation. However, they are different devices with different part numbers.

Individual logic gates are not manufactured in the FCT family. The simplest FCT logic element is a 74FCT138T decoder, which has six inputs, eight outputs, and contains the equivalent of about a dozen 4-input gates internally. Comparing its propagation delay and power consumption in Table.7 with the corresponding HCT and VHCT numbers in Table.3, the FCT-T family is superior in both speed and power dissipation. When comparing, note that FCT-T manufacturers specify only maximum, not typical propagation delays.

Unlike other CMOS families, FCT-T does not have a CPD specification. Instead, it has an ICCD specification, where I_CCD - Dynamic power supply current, in units of mA/MHz which is the amount of additional power supply current that flows when one input is changing at the rate of 1 MHz. The ICCD specification gives the same information as CPD, but in a different way.

The circuit’s internal power dissipation due to transitions at a given frequency f can be calculated by the formula

Thus, ICCD/VCC is algebraically equivalent to the CPD specification of other CMOS families. FCT-T also has a DICC specification for the extra quiescent current that is consumed with nonideal HIGH inputs.

Data Sheets and Specifications

DATA SHEETS AND SPECIFICATIONS

The manufacturers of real-world devices provide data sheets that specify the devices’ logical and electrical characteristics. The electrical specifications portion of a minimal data sheet for a simple CMOS device, the 54/74HC00 quadruple NAND gate, is shown in Table.1. Different manufacturers typically specify additional parameters, and they may vary in how they specify even the “standard” parameters shown in the table.

Table.1: Manufacturer’s Data sheet for a typical CMOS device, the 54/74HC00 quad NAND gate

They usually also show the test circuits and waveforms that they use to define various parameters, as shown in Fig.1, which contains information for some parameters in addition to those used with the 54/74HC00. As a logic designer, we need this knowledge to create reliable and robust real-world circuits and systems.

Fig.1: Test Circuits and Waveforms for HC – series Logic

ELECTRICAL BEHAVIOR OF CMOS CIRCUITS

ELECTRICAL BEHAVIOR OF CMOS CIRCUITS

A circuit or system designer must provide in a number of areas adequate engineering design margins - insurance that the circuit will work properly even under the worst of conditions.

The Circuit behavior is studied based on the following:

1.   Logic voltage levels

CMOS devices operating under normal conditions are guaranteed to produce output voltage levels within well-defined LOW and HIGH ranges based on LOW and HIGH input voltage levels over somewhat wider ranges. CMOS manufacturers specify these ranges and operating conditions very carefully to ensure compatibility among different devices in the same family, and to provide a degree of interoperability among devices in different families.

2.   DC noise margins

Nonnegative DC noise margins ensure that the highest LOW voltage produced by an output is always lower than the highest voltage that an input can reliably interpret as LOW, and that the lowest HIGH voltage produced by an output is always higher than the lowest voltage that an input can reliably interpret as HIGH.

3.   Fanout

This refers to the number and type of inputs that are connected to a given output. If too many inputs are connected to an output, the DC noise margins of the circuit may be inadequate. Fanout may also affect the speed at which the output changes from one state to another.

4.   Speed

The time that it takes a CMOS output to change from the LOW state to the HIGH state, or vice versa, depends on both the internal structure of the device and the characteristics of the other devices that it drives, even to the extent of being affected by the wire or printed-circuit-board traces connected to the output. Two separate components of “speed” exist i.e., transition time and propagation delay.

5.   Power consumption

The power consumed by a CMOS device depends on a number of factors, including its internal structure, the input signals that it receives, the other devices that it drives, and how often its output changes between LOW and HIGH.

6.   Noise

The main reason for providing engineering design margins is to ensure proper circuit operation in the presence of noise. Noise can be generated by a number of sources like Cosmic rays, Magnetic fields from nearby machinery, Power-supply disturbances, the switching action of the logic circuits themselves.

7.   Electrostatic discharge

The CMOS device can be damaged just by touching it due to electrostatic discharge.

8.   Open-drain outputs

Some CMOS outputs omit the usual p-channel pullup transistors. In the HIGH state, such outputs are effectively a “no-connection,” which is useful in some applications.

9.   Three-state outputs

Some CMOS devices have an extra “output enable” control input that can be used to disable both the p-channel pull-up transistors and the n-channel pull-down transistors. Many such device outputs can be tied together to create a multisource bus, as long as the control logic is arranged so that at most one output is enabled at a time.