Transistor-Transistor Logic

Transistor-Transistor Logic

The most commonly used bipolar logic family, there are many different TTL families, with a range of speed, power consumption, and other characteristics. Eg., Low-power Schottky (LS or LS-TTL) which use basically the same logic levels as the TTL-compatible CMOS families. For TTL circuit behavior: LOW 0–0.8 volts. HIGH 2.0–5.0 volts.

Basic TTL NAND Gate

The circuit diagram for a two-input LS-TTL NAND gate, part number 74LS00, is shown in Fig.15. The NAND function is obtained by combining a diode AND gate with an inverting buffer amplifier. The circuit’s operation depends on three parts i.e., Diode AND gate and input protection, Phase splitter and Output stage.

Diodes D1X and D1Y and resistor R1 form a diode AND gate. Clamp diodes D2X and D2Y do nothing in normal operation, but limit undesirable negative excursions on the inputs to a single diode drop. Such negative excursions may occur on HIGH-to-LOW input transitions as a result of transmission-line effects.

Transistor Q2 and the surrounding resistors form a phase splitter that controls the output stage. Depending on whether the diode AND gate produces a “low” or a “high” voltage at VA, Q2 is either cut off or turned on.

Fig.15: Two - input LS-TTL NAND gate (a) Circuit diagram (b) Function Table (c) Truth Table (d) Logic Symbol

The output stage has two transistors, Q4 and Q5, only one of which is on at any time. The TTL output stage is sometimes called a totem-pole or push-pull output. Similar to the p-channel and n-channel transistors in CMOS, Q4 and Q5 provide active pull-up and pull-down to the HIGH and LOW states, respectively.

The functional operation of the TTL NAND gate is summarized in Fig.15 (b). The gate does indeed perform the NAND function, with the truth table and logic symbol shown in (c) and (d).

TTL NAND gates can be designed with any desired number of inputs simply by changing the number of diodes in the diode AND gate in the figure. Commercially available TTL NAND gates have as many as 13 inputs. A TTL inverter is designed as a 1-input NAND gate, omitting diodes D1Y and D2Y in Fig.15.

Since the output transistors Q4 and Q5 are normally complementary—one

ON and the other OFF—you might question the purpose of the 120Ω resistor R5 in the output stage. A value of 0Ω would give even better driving capability in the HIGH state, certainly true from a DC point of view.

But when the TTL output is changing from HIGH to LOW or vice versa, there is a short time when both transistors may be on. The purpose of R5 is to limit the amount of current that flows from VCC to ground during this time. Even with a 120 Ω resistor in the TTL output stage, higher-than-normal currents called current spikes flow when TTL outputs are switched. These are similar to the current spikes that occur when high-speed CMOS outputs switch.

(Reliable circuits require decoupling capacitors between VCC and ground, distributed throughout the circuit so that there is a capacitor within an inch or so of each chip. Decoupling capacitors supply the instantaneous current needed during transitions.)

Fig.16: A TTL output driving a TTL input LOW

For the input signals to a TTL gate as ideal voltage sources. Fig.16 shows the operation when a TTL input is driven LOW by the output of another TTL gate. Transistor Q5A in the driving gate is ON and thereby provides a path to ground for the current flowing out of the diode D1XB in the driven gate. When current flows into a TTL output in the LOW state, the output is said to be sinking current.

Fig.17: A TTL output driving a TTL input HIGH

Fig.17 shows the same circuit with a HIGH output where Q4A in the driving gate is turned on enough to supply the small amount of leakage current flowing through reverse-biased diodes D1XB and D2XB in the driven gate. When current flows out of a TTL output in the HIGH state, the output is said to be sourcing current.

Logic Levels and Noise Margins

Consider TTL signals between 0 and 0.8 V to be LOW, and signals between 2.0 and 5.0 V to be HIGH.

V_OHmin - The minimum output voltage in the HIGH state, 2.7 V for most TTL

families.

V_IHmin - The minimum input voltage guaranteed to be recognized as a HIGH, 2.0 V for all TTL families.

Fig.18: Noise margins for popular TTL logic families (74LS,74S, 74ALS, 74AS, 74F)

V_ILmax - The maximum input voltage guaranteed to be recognized as a LOW, 0.8 V for most TTL families.

V_OLmax - The maximum output voltage in the LOW state, 0.5 V for most families.

These noise margins are shown in Fig.18. In the HIGH state, the VOHmin specification of most TTL families exceeds VIHmin by 0.7 V, so TTL has a DC noise margin of 0.7 V in the HIGH state, i.e., it takes at least 0.7 V of noise to corrupt a worst-case HIGH output into a voltage that is not guaranteed to be recognizable as a HIGH input. In the LOW state, however, VILmax exceeds VOLmax by only 0.3 V, so the DC noise margin in the LOW state is only 0.3 V. In general, TTL and TTL-compatible circuits tend to be more sensitive to noise in the LOW state than in the HIGH state.

Fanout

fanout is a measure of the number of gate inputs that are connected to (and driven by) a single gate output. The DC fanout of CMOS outputs driving CMOS inputs is virtually unlimited, because CMOS inputs require almost no current in either state, HIGH or LOW. But for TTL inputs, there are very definite limits on the fanout of TTL or CMOS outputs driving TTL inputs.

As in CMOS, the current flow in a TTL input or output lead is defined to be positive if the current actually flows into the lead, and negative if current flows out of the lead. As a result, when an output is connected to one or more inputs, the algebraic sum of all the input and output currents is 0.

The amount of current required by a TTL input depends on whether the input is HIGH or LOW, and is specified by two parameters:

IILmax - The maximum current that an input requires to pull it LOW. Form Fig.16, positive current is actually flowing from VCC, through R1B, through diode D1XB, out of the input lead, through the driving output transistor Q5A, and into ground. Since current flows out of a TTL input in the LOW state, IILmax has a negative value. Most LS-TTL inputs have IILmax = -0.4 mA, which is sometimes called a LOW-state unit load for LS-TTL.

IIHmax - The maximum current that an input requires to pull it HIGH. As shown in Fig.17, positive current flows from VCC, through R5A and Q4A of the driving gate, and into the driven input, where it leaks to ground through reversed-biased diodes D1XB and D2XB. Since current flows into a TTL input in the HIGH state, IIHmax has a positive value. Most LS-TTL inputs have IIHmax = 20 mA, which is sometimes called a HIGH-state unit load for LS-TTL.

Like CMOS outputs, TTL outputs can source or sink a certain amount of current depending on the state, HIGH or LOW:

IOLmax The maximum current an output can sink in the LOW state while maintaining an output voltage no more than VOLmax. Since current flows into the output, IOLmax has a positive value, 8 mA for most LS-TTL outputs.

IOHmax The maximum current an output can source in the HIGH state while maintaining an output voltage no less than VOHmin. Since current flows out of the output, IOHmax has a negative value, -400 mA for most LSTTL outputs.

The value of IOLmax for typical LS-TTL outputs is exactly 20 times the absolute value of IILmax. As a result, LS-TTL is said to have a LOW state fanout of 20, because an output can drive up to 20 inputs in the LOW state.

Similarly, the absolute value of IOHmax is exactly 20 times IIHmax, so LS-TTL is said to have a HIGH-state fanout of 20 also. The overall fanout is the lesser of the LOW- and HIGH-state fanouts.

Loading a TTL output with more than its rated fanout has the same deleterious effects i.e, DC noise margins may be reduced or eliminated, transition times and delays may increase, and the device may overheat.

In general, two calculations must be carried out to confirm that an output is

not being overloaded:

HIGH state - The IIHmax values for all of the driven inputs are added. This sum must be less than or equal to the absolute value of IOHmax for the driving output.

LOW state - The IILmax values for all of the driven inputs are added. The absolute value of this sum must be less than or equal to IOLmax for the driving output.

Eg., A system in which a certain LS-TTL output drives ten LS-TTL and three S-TTL gate inputs.

In the HIGH state, a total of 10 × 20 + 3 × 50 mA = 350 mA is required. This is within an LS-TTL output’s HIGH-state current-sourcing capability of 400 mA.

But in the LOW state, a total of 10 × 0.4 + 3 × 2.0 mA = 10.0 mA is required. This is more than an LS-TTL output’s LOW-state current-sinking capability of 8 mA, so the output is overloaded.

Unused Inputs

Unused inputs of TTL gates can be handled in the same way as CMOS gates i.e., unused inputs may be tied to used ones, or unused inputs may be pulled HIGH or LOW as is appropriate for the logic function.

The resistance value of a pull-up or pull-down resistor is more critical with TTL gates than CMOS gates, because TTL inputs draw significantly more current, especially in the LOW state. If the resistance is too large, the voltage drop across the resistor may result in a gate input voltage beyond the normal LOW or HIGH range.

Eg., consider the pull-down resistor shown in Fig.19. The pull-down resistor must sink 0.4 mA of current from each of the unused LS-TTL inputs that it drives. Yet the voltage drop across the resistor must be no more than 0.5 V in order to have a LOW input voltage no worse than that produced by a normal gate output. If the resistor drives n LS-TTL inputs, then we must have

 

Fig.19: Pull-down resistor for TTL inputs

Thus, if the resistor must pull 10 LS-TTL inputs LOW, then we must have Rpd <0.5 / (10 × 4 × 10-3), or Rpd < 125 W. Similarly, consider the pull-up resistor shown in Fig.20.

Fig.20: Pull-up resistor for TTL inputs

It must source 20 mA of current to each unused input while producing a HIGH voltage no worse than that produced by a normal gate output, 2.7 V. Therefore, the voltage drop across the resistor must be no more than 2.3 V; if n LS-TTL input are driven, we must have

Thus, if 10 LS-TTL inputs are pulled up, then Rpu < 2.3 / (10 × 20×10-6), or

Rpu < 11.5 KW.

Additional TTL Gate Types

Although the NAND gate is the “workhorse” of the TTL family, other types of gates can be built with the same general circuit structure. The circuit diagram for an LS-TTL NOR gate is shown in Fig.21.

Fig.21 Two-input LS-TTL NOR Gate (a) Circuit Diagram (b) Function Table (c) Truth Table (d) Logic Symbol

If either input X or Y is HIGH, the corresponding phase-splitter transistor Q2X or Q2Y is turned on, which turns off Q3 and Q4 while turning on Q5 and Q6, and the output is LOW. If both inputs are LOW, then both phase-splitter transistors are off, and the output is forced HIGH. This functional operation is summarized in Fig.21 (b).

The LS-TTL NOR gate’s input circuits, phase splitter, and output stage are almost identical to those of an LS-TTL NAND gate. The difference is that an LSTTL NAND gate uses diodes to perform the AND function, while an LS-TTL NOR gate uses parallel transistors in the phase splitter to perform the OR function.

The speed, input, and output characteristics of a TTL NOR gate are comparable to those of a TTL NAND. However, an n-input NOR gate uses more transistors and resistors and is thus more expensive in silicon area than an n input NAND. Also, internal leakage current limits the number of Q2 transistors that can be placed in parallel, so NOR gates have poor fan-in. (The largest discrete TTL NOR gate has only 5 inputs, compared with a 13-input NAND.) As a result, NOR gates are less commonly used than NAND gates in TTL designs. The most “natural” TTL gates are inverting gates like NAND and NOR. Non-inverting TTL gates include an extra inverting stage, typically between the input stage and the phase splitter. As a result, non-inverting TTL gates are typically larger and slower than the inverting gates on which they are based.

Like CMOS, TTL gates can be designed with three-state outputs. Such gates have an “output-enable” or “output-disable” input that allows the output to be placed in a high-impedance state where neither output transistor is turned on. Some TTL gates are also available with open-collector outputs. Such gates omit the entire upper half of the output stage in Fig.15, so that only passive pull-up to the HIGH state is provided by an external resistor. The applications and required calculations for TTL open-collector gates are similar to those for CMOS gates with open-drain outputs.