Thursday, October 15, 2015

Multiplexers

Unit-V
COMBINATIONAL LOGIC DESIGN
Multiplexers

A multiplexer is a digital switch—it connects data from one of n sources to its output. Figure.1(a) shows the inputs and outputs of an n-input, b-bit multiplexer.

 

Figure 1: Multiplexer Structure (a) inputs and outputs (b) Functional Equivalent

There are n sources of data, each of which is b bits wide, and there are b output bits. In typical commercially available multiplexers, n = 1, 2, 4, 8, or 16, and b = 1, 2, or 4. There are s inputs that select among the n sources, so s = [log2n]. An enable input EN allows the multiplexer to “do its thing”; when EN = 0, all of the outputs are 0. A multiplexer is often called a mux for short. Figure.1(b) shows a switch circuit that is roughly equivalent to the multiplexer.


 However, unlike a mechanical switch, a multiplexer is a unidirectional device: information flows only from inputs (on the left) to outputs (on the right).

In the general logic equation for a multiplexer output, the summation symbol represents a logical sum of product terms. Variable iY is a particular output bit (1 ≤ i b), and variable iDj is input bit i of source j (0 ≤ j n - 1). Mj represents minterm j of the s select inputs. Thus, when the multiplexer is enabled and the value on the select inputs is j, each output iY equals the corresponding bit of the selected input, iDj.

Multiplexers are obviously useful devices in any application in which data must be switched from multiple sources to a destination. A common application in computers is the multiplexer between the processor’s registers and its arithmetic logic unit (ALU). Eg., consider a 16-bit processor in which each instruction has a 3-bit field that specifies one of eight registers to use. This 3-bit field is connected to the select inputs of an 8-input, 16-bit multiplexer. The multiplexer’s data inputs are connected to the eight registers, and its data outputs are connected to the ALU to execute the instruction using the selected register.

Standard MSI Multiplexers

The sizes of commercially available MSI multiplexers are limited by the number of pins available in an inexpensive IC package. Commonly used muxes come in 16-pin packages.

Figure 2: The 74x151 8-input, 1-bit multiplexer (a) Logic Diagram including pin numbers for a standard 16-pin dual-in line package (b) traditional Logic Symbol

The 74x151, shown in Figure.2 selects among eight 1-bit inputs. The select inputs are named C, B, and A, where C is most significant numerically. The enable input EN_L is active low; both active-high (Y) and active-low (Y_L) versions of the output are provided. The 74x151’s truth table is shown in Table.1. In the 74x151’s table, only a few of the inputs are listed under the “Inputs” heading. Each output is specified as 0, 1, or a simple logic function of the remaining inputs (e.g., D0 or D0’), which saves eight columns and eight rows in the table, and presents the logic function more clearly than a larger table would.

Table.1: Truth Table for a 74x151 8-input, 1-bit multiplexer


Program Code:

Library ieee;
Use ieee.std_logic_1164.all;

Entity mux74x151 is
Port( EN_L: in std_logic;
S: in std_logic_vector(2 downto 0);
D: in std_logic_vector(7 downto 0);
Y,Y_L: out std_logic);
End mux74x151;

Architecture dataflow of mux74x151 is
Signal Y1: std_logic;
Begin
          with S select  Y1<=    D(7) when “111”,
                             D(6) when “110”,
                             D(5) when “101”,
                             D(4) when “100”,
D(3) when “011”,
D(2) when “010”,
D(1) when “001”,
D(0) when “000”,
                             ‘0’ when others;
          Y<=Y1 when EN_L=‘0’ else ‘0’;
          Y_L<=not y;
End dataflow;

Architecture behav of mux74x151 is
Begin
Process(EN_L, S, D)
Begin
Case S is
When “111” =>   Y1<=    D(7) ;
When “110” =>   Y1<=    D(6) ;
When “101” =>   Y1<=    D(5) ;
When “100” =>   Y1<=    D(4) ;
When “011” =>   Y1<=    D(3) ;
When “010” =>   Y1<=    D(2) ;
When “001” =>   Y1<=    D(1) ;
When “000” =>   Y1<=    D(0) ;
When others =>   Y1<=‘0’;
End case;
If (EN_L=‘0’) then
Y<=Y1;
Else
Y<=‘0’;
End if;
Y_L<=not Y;
End process;
End behav;

The 74x157 is shown in Figure.3, which selects between two 4-bit inputs. The select input is S, the active-low enable input is G_L and the data sources are named A and B instead of D0 and D1. The extended truth-table notation makes the 74x157’s description very compact, as shown in Table.2.

Table 2: Truth Table for a 74x157 2-input, 4-bit multiplexer



Figure 3: The 74x157 2-input, 4-bit multiplexer (a) Logic Diagram including pin numbers for a standard 16-pin dual in-line package (b) Traditional Logic Symbol

Program Code:

Library ieee;
Use ieee.std_logic_1164.all;

Entity mux74x157 is
Port( EN_L,S: in std_logic;
A,B: in std_logic_vector(4 downto 1);
Y: out std_logic_Vector(4 downto 1));
End mux74x157;

Architecture dataflow of mux74x157 is
Signal y1: std_logic_vector(4 down to 1);
Begin
with S select  Y1<=    A when ‘0’,
                                  B when ‘1’,
                                  “0000” when others;
y<=y1 when G_L=‘1’ else “0000”;
End dataflow;

The intermediate between the 74x151 and 74x157 is the 74x153, a 4-input, 2-bit multiplexer, whose logic symbol is shown in Figure.4, has separate enable inputs (1G, 2G) for each bit and its function is shown in Table.3.

Table 3: Truth Table for a 74x153 4-input, 2-bit multiplexer
                               


Figure 4: Traditional Symbol for the 74x153
Some multiplexers have three-state outputs. The enable input of such a multiplexer, instead of forcing the outputs to zero, forces them to the Hi-Z state. Eg., the 74x251 is identical to the ’151 in its pinout and its internal logic design, except that Y and Y_L are three-state outputs. When the EN_L input is negated, instead of forcing the outputs to be negated, it forces the outputs into the high-Z state. Similarly, the 74x253 and 74x257 are three-state versions of the ’153 and ’157. The three-state outputs are especially useful when n-input muxes are combined to form larger muxes.

Program Code

Library ieee;
Use ieee.std_logic_1164.all;

Entity mux74x153 is
Port( G_L,S: in std_logic_vector(1 downto 0);
C1,C2: in std_logic_vector(3 downto 0);
Y: out std_logic_Vector(1 downto 0));
End mux74x153;

Architecture behavioral of mux74x153 is
Signal y1: std_logic_vector(1 downto 0);
Begin
Process(G_L,S,C1,C2)
Begin
If (G_L=“00”) then
If (S=“00”) then
Y1(1)<= C1(0);
Y1(0)<= C2(0);
Elsif (S=“01” ) then
Y1(1)<= C1(1);
Y1(0)<= C2(1);
Elsif (S=“10” ) then
Y1(1)<= C1(2);
Y1(0)<= C2(2);
Elsif (S=“11” ) then
Y1(1)<= C1(3);
Y1(0)<= C2(3);
End if;
Els if(G_L=“01” ) then
If (S=“00”) then
Y1(1)<= C1(0);
Y1(0)<= ‘0’;
Elsif (S=“01” ) then
Y1(1)<= C1(1);
Y1(0)<= ‘0’;
Elsif (S=“10” ) then
Y1(1)<= C1(2);
Y1(0)<= ‘0’;
Elsif (S=“11” ) then
Y1(1)<= C1(3);
Y1(0)<= ‘0’;
End if;
Els if(G_L=“10” ) then
If (S=“00”) then
Y1(1)<= ‘0’;
Y1(0)<= C2(0);
Elsif (S=“01” ) then
Y1(1)<= ‘0’;
Y1(0)<= C2(1);
Elsif (S=“10” ) then
Y1(1)<= ‘0’;
Y1(0)<= C2(2);
Elsif (S=“11” ) then
Y1(1)<= ‘0’;
Y1(0)<= C2(3);
End if;
Elsif (G_L=“11”) then
Y1=“00”;
 end if;
End process;
End behavioral;

Expanding Multiplexers

Seldom does the size of an MSI multiplexer match the characteristics of the problem at hand. Eg., an 8-input, 16-bit multiplexer might be used in the design of a computer processor, this function could be performed by 16 74x151 8-input, 1-bit multiplexers or equivalent ASIC cells, each handling one bit of all the inputs and the output. The processor’s 3-bit register-select field would be connected to the A, B, and C inputs of all 16 muxes, so they would all select the same register source at any given time.

The device that produces the 3-bit register-select field in this example must have enough fanout to drive 16 loads. With 74LS-series ICs this is possible because typical devices have a fanout of 20 LS-TTL loads. Still, it is fortunate that the ’151 was designed so that each of the A, B, and C inputs presents only one LS-TTL load to the circuit driving it. Theoretically, the ’151 could have been designed without the first rank of three inverters shown on the select inputs in Figure.5, but then each select input would have presented five LS-TTL loads, and the drivers in the register-select application would need a fanout of 80.

Also the multiplexers can be expanded with the number of data sources. Eg. For a 32-input, 1-bit multiplexer, Figure.5 shows five select bits are required. A 2-to-4 decoder (one-half of a 74x139) decodes the two high-order select bits to enable one of four 74x151 8-input multiplexers. Since only one ’151 is enabled at a time, the ’151 outputs can simply be ORed to obtain the final output.

Figure 5: Combining 74x151s to make a 32-to-1 multiplexer.
Program Code
Library ieee;
Use ieee.std_logic_1164.all;

Entity mux32to1 is
Port(XEN_L: in std_logic;
XA: in std_logic_vector(4 downto 0);
X: in std_logic_vector(31 downto 0);
XOUT:out std_logic);
End mux32to1;

Architectural structural of mux32to1 is

Component dec74x139 is
Port(G_L: in std_logic;
A: in std_logic_vector(1 downto 0);
Y:out std_logic_vector(3 downto 0));
End component;

Component IC74x151 is
Port(EN_L: in std_logic;
S: in std_logic_vector(2 downto 0);
D: in std_logic_vector(7 downto 0);
Y,Y_L: out std_logic);
End component;

Component IC74x20 is
Port(D_L: in std_logic_vector(3 downto 0);
Y: out std_logic);
End component;

Signal EN_L, XO_L: std_logic_vector(3 downto 0);

Begin
U1: IC74139  port map(XEN_L,XA(3),XA(4),EN_L(3 downto 0));
U2: IC74x151  port map(EN_L(0), XA(2 downto 0),X(7 downto 0), OPEN, XO_L(0));
U3: IC74x151  port map(EN_L(1), XA(2 downto 0),X(15 downto 8), OPEN, XO_L(1));
U4: IC74x151  port map(EN_L(2), XA(2 downto 0),X(23 downto 16), OPEN, XO_L(2));
U5: IC74x151  port map(EN_L(3), XA(2 downto 0),X(31 downto 24), OPEN, XO_L(3));
U6: IC74x20 port map(XO_L, XOUT);
End structural;

The 32-to-1 multiplexer can also be built using 74x251s, this circuit is identical to Figure.6, except that the output NAND gate is eliminated. Instead, the Y (and, if desired, Y_L) outputs of the four ’251s are simply tied together. The ’139 decoder ensures that at most one of the ’251s has its threestate outputs enabled at any time. If the ’139 is disabled (XEN_L is negated), then all of the ’251s are disabled, and the XOUT and XOUT_L outputs are undefined. However, if desired, resistors may be connected from each of these signals to +5 volts to pull the output HIGH in this case.


Figure 6: A multiplexer driving a bus and a demultiplexer receiving the bus (a) Switch equivalent (b) Block Diagram Symbols

Multiplexers, Demultiplexers, and Buses

A multiplexer can be used to select one of n sources of data to transmit on a bus. At the far end of the bus, a demultiplexer can be used to route the bus data to one of m destinations. Such an application, using a 1-bit bus, is depicted in terms of our switch analogy in Figure.6(a). In fact, block diagrams for logic circuits often depict multiplexers and demultiplexers using the wedge-shaped symbols in (b), to suggest visually how a selected one of multiple data sources gets directed onto a bus and routed to a selected one of multiple destinations. The function of a demultiplexer is just the inverse of a multiplexer’s. Eg., a 1-bit, n-output demultiplexer has one data input and s inputs to select one of n = 2s data outputs. In normal operation, all outputs except the selected one are 0; the selected output equals the data input. This definition may be generalized for a b-bit, n-output demultiplexer; such a device has b data inputs, and its s select inputs choose one of n = 2s sets of b data outputs.

A binary decoder with an enable input can be used as a demultiplexer, as shown in Figure.7. The decoder’s enable input is connected to the data line, and its select inputs determine which of its output lines is driven with the data
bit. The remaining output lines are negated. Thus, the 74x139 can be used as a 2-bit, 4-output demultiplexer with active-low data inputs and outputs, and the 74x138 can be used as a 1-bit, 8-output demultiplexer. In fact, the manufacturer’s catalog typically lists these ICs as “decoders/demultiplexers.”


Figure 7: Using a 2-to-4 binary decoder as a 1-bit, 4-output demultiplexer (a) generic Decoder (b) 74x139



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