COMPARATORS

Unit-V

COMBINATIONAL LOGIC DESIGN

Comparators

Comparing two binary words for equality is a commonly used operation in computer systems and device interfaces. A circuit that compares two binary words and indicates whether they are equal is called a comparator.

Some comparators interpret their input words as signed or unsigned numbers and also indicate an arithmetic relationship (greater or less than) between the words. These devices are often called magnitude comparators.

Comparator Structure

EXCLUSIVE OR and EXCLUSIVE NOR gates may be viewed as 1-bit comparators. Figure 1(a) shows an interpretation of the 74x86 XOR gate as a 1-bit comparator. The active-high output, DIFF, is asserted if the inputs are different. The outputs of four XOR gates are ORed to create a 4-bit comparator in (b). The DIFF output is asserted if any of the input-bit pairs are different. Given enough XOR gates and wide enough OR gates, comparators with any number of input bits can be built.

Figure 1: Comparators using 74x86 (a) 1-bit Comparator (b) 4-bit Comparator

Iterative Circuits

An iterative circuit is a special type of combinational circuit as shown in Figure 2. The circuit contains n identical modules, each of which has both primary inputs and outputs and cascading inputs and outputs. The leftmost cascading inputs are called boundary inputs and are connected to fixed logic values in most iterative circuits. The rightmost cascading outputs are called boundary outputs and usually provide important information.

Iterative circuits are well suited to problems that can be solved by a simple iterative algorithm:

1. Set C0 to its initial value and set i to 0.

2. Use Ci and PIi to determine the values of POi and Ci+1.

3. Increment i.

4. If i < n, go to step 2.

In an iterative circuit, the loop of steps 2–4 is “unwound” by providing a separate combinational circuit that performs step 2 for each value of i.

Figure 2: General Structure of an iterative Combinational Circuit

Eg: The 74x85 4-bit comparator and the 74x283 4-bit adder are examples of MSI circuits that can be used as the individual modules in a larger iterative circuit.

An Iterative Comparator Circuit

Two n-bit values X and Y can be compared one bit at a time using a single bit EQi at each step to keep track of whether all of the bit-pairs have been equal so far:

1. Set EQ0 to 1 and set i to 0.

2. If EQi is 1 and Xi and Yi are equal, set EQ_{i +1} to 1. Else set EQ_i+1 to 0.

3. Increment i.

4. If i < n, go to step 2.

Figure 3: An iterative Comparator Circuit (a) Module for one bit (b) Complete Circuit

Figure 3 shows a corresponding iterative circuit, this circuit has no primary outputs; the boundary output is our interest. Other iterative circuits, such as the ripple adder, have primary outputs of interest. When a choice between the iterative comparator circuit and one of the parallel comparators, then prefer the parallel comparator. The iterative comparator saves little if any cost, and it’s very slow because the cascading signals need time to “ripple” from the leftmost to the rightmost module. Iterative circuits that process more than one bit at a time, using modules like the 74x85 4-bit comparator and 74x283 4-bit adder, are much more likely to be used in practical designs.

Figure 4: Traditional Logic Symbol for the 74x85 4-bit comparator

Behavioral VHDL program for comparing 4-bit integers using 74x85.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

entity comp74x85 is

port ( A, B: in STD_LOGIC_VECTOR(3 downto 0);

ALTBIN, AGTBIN, AEQBIN: in STD_LOGIC;

ALTBOUT, AGTBOUT, AEQBOUT: out STD_LOGIC);

end comp74x85;

architecture behavior of comp74x85 is

begin

process (A, B, ALTBIN, AGTBIN, AEQBIN)

begin

ALTBIN<= '0'; 

AGTBIN<= '0'; 

AEQBIN<= '0'; 

if A < B then 

ALTBIN <= '1';

AGTBIN<= '0'; 

AEQBIN<= '0'; 

else if A > B then 

ALTBIN<= '0'; 

AGTBIN<= '1'; 

AEQBIN<= '0'; 

else

ALTBIN<= '0'; 

AGTBIN<= '0'; 

AEQBIN<= '1'; 

end if;

end if;

end process;

end behavior;

Standard MSI Comparators

Comparator applications are common enough that several MSI comparators have been developed commercially. The 74x85 is a 4-bit comparator with the logic symbol shown in Figure 4. It provides a greater-than output (AGTBOUT) and a less-than output (ALTBOUT) as well as an equal output (AEQBOUT). The ’85 also has cascading inputs (AGTBIN, ALTBIN, and AEQBIN) for combining multiple ’85s to create comparators for more than four bits. Both the cascading inputs and the outputs are arranged in a 1-out-of-3 code, since in normal operation exactly one input and one output should be asserted.

Figure 5: Traditional Logic Symbol for the 74x682 8-bit Comparator

Behavioral VHDL program for comparing 8-bit integers using 74x682.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

entity comp74x682 is

port ( P,Q: in STD_LOGIC_VECTOR(7 downto 0);

PEQQ_L, PGTQ_L: out STD_LOGIC);

end comp74x682;

architecture behavior of comp74x682 is

begin

process (P,Q)

begin

if P>Q then 

PGTQ_L <= '0';

PEQQ_L<= '1'; 

else if P = Q then 

PGTQ_L <= '1';

PEQQ_L<= '0'; 

else

PGTQ_L <= '1';

PEQQ_L<= '1'; 

end if;

end if;

end process;

end behavior;

Figure 6: A 12-bit Comparator using 74x85s

Behavioral VHDL program for comparing 12-bit integers using 74x85.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

entity comp12bit is

port ( XD,YD: in STD_LOGIC_VECTOR(11 downto 0);

XLTY,XEQY,XGTY: out STD_LOGIC);

end comp12bit;

architecture structural of comp74x85 is

signal XLTY4, XEQY4, XGTY4, XLTY8, XGTY8, XEQY8: STD_LOGIC; 

begin

U1: comp74x85 port map(XD[3 downto 0),YD(3 downto 0),'0','0','1',XLTY4,XGTY4,XEQY4);

U2: comp74x85 port map(XD[7 downto 4),YD(7 downto 4),XLTY4,XGTY4,XEQY4,XLTY8,XGTY8,XEQY8);

U3: comp74x85 port map(XD[11 downto 8),YD(11 downto 8),XLTY8,XGTY8,XEQY8,XLTY,XGTY,XEQY);

end structural; 

The cascading inputs are defined so the outputs of an ’85 that compares less-significant bits are connected to the inputs of an ’85 that compares more-significant bits, as shown in Figure 6 for a 12-bit comparator. Each ’85 develops its cascading outputs roughly according to the following pseudo-logic equations:

The parenthesized sub-expressions above are not normal logic expressions, but indicate an arithmetic comparison that occurs between the A3–A0 and B3–B0 inputs. In other words, AGTBOUT is asserted if A > B or if A = B and AGTBIN is asserted (if the higher-order bits are equal, then the lower-order bits are considered). The arithmetic comparisons can be expressed using normal logic expressions, Eg.,

Such expressions must be substituted into the pseudo-logic equations above to obtain genuine logic equations for the comparator outputs. Several 8-bit MSI comparators are also available. The simplest of these is the 74x682, whose logic symbol is shown in Figure 6 and whose internal logic diagram is shown in Figure 7.

Figure 7: Logic Diagram for the 74x682 8-bit comparator including pin numbers for a standard 20-pin dual-in-line package

The top half of the circuit checks the two 8-bit input words for equality. Each XNOR-gate output is asserted if its inputs are equal, and the PEQQ_L output is asserted if all eight input-bit pairs are equal. The bottom half of the circuit compares the input words arithmetically, and asserts /PGTQ if P[7–0] > Q[7–0]. Unlike the 74x85, the 74x682 does not have cascading inputs. Also unlike the ’85, the ’682 does not provide a “less than” output. However, any desired condition, including ≤ and ≥, can be formulated as a function of the PEQQ_L and PGTQ_L outputs, as shown in Figure 8.

Figure 8: Arithmetic Conditions derived from 74x682 Outputs

Behavioral VHDL program for deriving arithmetic conditions from 74x682 Outputs.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

entity arith74x682 is

port ( P,Q: in STD_LOGIC_VECTOR(7 downto 0);

PNEQ, PEQQ, PGTQ, PGEQ, PLEQ, PLTQ: out STD_LOGIC);

end comp74x682;

architecture stuctural of arith74x682 is

PEQQ_L,PGTQ_L: STD_LOGIC;

begin

U1: comp74x682 port map(P,Q, PEQQ_L, PGTQ_L);

assign PNEQ=PEQQ_L;

--not, nand and and are built-in primitives of VHDL

U2: not portmap(PEQQ,PEQQ_L);

U3: not port map(PGTQ,PGTQ_L);

U4: nand port map(PGEQ,PEQQ_L, PGTQ_L);

assign PLEQ=PGTQ_L;

U5: and port map(PLTQ,PEQQ_L,PGTQ_L);

end structural;

Behavioral VHDL program for comparing 8-bit unsigned integers

library IEEE;

use IEEE.std_logic_1164.all;

entity vc is

port (

A, B: in STD_LOGIC_VECTOR (7 downto 0);

EQ, NE, GT, GE, LT, LE: out STD_LOGIC

);

end vc;

architecture vc_arch of vc is

begin

process (A, B)

begin

EQ <= '0'; NE <= '0'; GT <= '0'; GE <= '0'; LT <= '0'; LE <= '0';

if A = B then EQ <= '1'; end if;

if A /= B then NE <= '1'; end if;

if A > B then GT <= '1'; end if;

if A >= B then GE <= '1'; end if;

if A < B then LT <= '1'; end if;

if A <= B then LE <= '1'; end if;

end process;

end vc_arch

Behavioral VHDL program for comparing 8-bit integers of various types.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

entity vcmpa is

port (

A, B: in UNSIGNED (7 downto 0);

C: in SIGNED (7 downto 0);

D: in STD_LOGIC_VECTOR (7 downto 0);

A_LT_B, B_GE_C, A_EQ_C, C_NEG, D_BIG, D_NEG: out STD_LOGIC

);

end vcmpa;

architecture vcmpa_arch of vcmpa is

begin

process (A, B, C, D)

begin

A_LT_B <= '0'; B_GE_C <= '0'; A_EQ_C <= '0'; C_NEG <= '0'; D_BIG <= '0'; D_NEG <= '0';

if A < B then A_LT_B <= '1'; end if;

if B >= C then B_GE_C <= '1'; end if;

if A = C then A_EQ_C <= '1'; end if;

if C < 0 then C_NEG <= '1'; end if;

if UNSIGNED(D) > 200 then D_BIG <= '1'; end if;

if SIGNED(D) < 0 then D_NEG <= '1'; end if;

end process;

end vcmpa_arch;