Monday, September 14, 2015

Unit-V: Combinational Logic Design - DECODERS

Unit-V
COMBINATIONAL LOGIC DESIGN

Decoders

A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. The input code generally has fewer bits than the output code, and there is a one-to one mapping from input code words into output code words. In a one-to-one mapping, each input code word produces a different output code word.

The general structure of a decoder circuit is shown in Figure 1. The enable inputs, if present, must be asserted for the decoder to perform its normal mapping function. Otherwise, the decoder maps all input code words into a single, “disabled,” output code word.

The most commonly used input code is an n-bit binary code, where an n-bit word represents one of 2n different coded values, normally the integers from 0 through 2n-1.

Sometimes an n-bit binary code is truncated to represent fewer than 2n values. Eg., in the BCD code, the 4-bit combinations 0000 through 1001 represent the decimal digits 0–9, and combinations 1010 through 1111 are not used.

The most commonly used output code is a 1-out-of-m code, which contains m bits, where one bit is asserted at any time. Hence, in a 1-out-of-4 code with active-high outputs, the code words are 0001, 0010, 0100, and 1000. With active-low outputs, the code words are 1110, 1101, 1011, and 0111.


Figure 1: Decoder Circuit Structure
Binary Decoders

The most common decoder circuit is an n-to-2n decoder or binary decoder, which has an n-bit binary input code and a 1-out-of-2n output code. A binary decoder is used when we need to activate exactly one of 2n outputs based on an n-bit input value.

Eg., Figure 2(a) shows the inputs and outputs and Table 1 is the truth table of a 2-to-4 decoder.


Figure 2: A 2-to-4 Decoder (a) Inputs and outputs (b) Logic Diagram

The input code word 1, I0 represents an integer in the range 0–3. The output code word Y3,Y2,Y1,Y0 has Yi equal to 1 if and only if the input code word is the binary representation of i and the enable input EN is 1. If EN is 0, then all of the outputs are 0. A gate-level circuit for the 2-to-4 decoder is shown in Figure 2(b). Each AND gate decodes one combination of the input code word I1,I0.

Table 1: Truth Table for 1 2-to-4 Binary Decoder


The binary decoder’s truth table introduces a “don’t-care” notation for input combinations. If one or more input values do not affect the output values for some combination of the remaining inputs, they are marked with an “x” for that input combination. This convention can greatly reduce the number of rows in the truth table, as well as make the functions of the inputs more clear.

The input code of an n-bit binary decoder need not represent the integers from 0 through 2n-1. Eg., Table 2 shows the 3-bit Gray-code output of a mechanical encoding disk with eight positions. The eight disk positions can be decoded with a 3-bit binary decoder with the appropriate assignment of signals to the decoder outputs, as shown in Figure 3.

Also, it is not necessary to use all of the outputs of a decoder, or even to decode all possible input combinations. Eg., a decimal or BCD decoder decodes only the first ten binary input combinations 0000–1001 to produce outputs Y0Y9.

Table 2: Position Encoding for a 3-bit Mechanical Encoding Disk


Figure 3: A 3-to-8 Binary Decoder used to decode a Gray Code

Structural Model

library IEEE;
use IEEE.std_logic_1164.all;

entity V2to4dec is
port (I0, I1, EN: in STD_LOGIC;
Y0, Y1, Y2, Y3: out STD_LOGIC);
end V2to4dec;

architecture structural of V2to4dec is
signal NOTI0, NOTI1: STD_LOGIC;

component inv
port (I: in STD_LOGIC;
       O: out STD_LOGIC);
end component;

component and3
port (I0, I1, I2: in STD_LOGIC;
O: out STD_LOGIC);
end component;

begin
U1: inv port map (I0,NOTI0);
U2: inv port map (I1,NOTI1);
U3: and3 port map (NOTI0,NOTI1,EN,Y0);
U4: and3 port map ( I0,NOTI1,EN,Y1);
U5: and3 port map (NOTI0, I1,EN,Y2);
U6: and3 port map ( I0, I1,EN,Y3);
end structural;

library IEEE;
use IEEE.std_logic_1164.all;

entity inv is
port (I: in STD_LOGIC;
       O: out STD_LOGIC);
end inv;

architecture dataflow of inv is
begin
O<=not I;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;

entity and3 is
port (I0,I1,I2: in STD_LOGIC;
       O: out STD_LOGIC);
end inv;

architecture dataflow of and3 is
begin
O<=I1 and (I2 and I3);
end dataflow;

Dataflow Model

library IEEE;
use IEEE.std_logic_1164.all;

entity V2to4dec is
port (E: in STD_LOGIC; -- enable input
I: in STD_LOGIC_VECTOR (1 downto 0); -- select inputs
Y: out STD_LOGIC_VECTOR (0 to 3) ); -- decoded outputs
end V2to4dec;

architecture dataflow of V2to4dec is
signal Y_i: STD_LOGIC_VECTOR (0 to 3);
begin
with I select Y_i <=
"0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when "11",
"0000" when others;
Y <= Y_i when EN = '1' else "0000";
end dataflow;

Behavioral Model

library IEEE;
use IEEE.std_logic_1164.all;

entity V2to4dec is
port (EN: in STD_LOGIC; -- enable input
I: in STD_LOGIC_VECTOR (1 downto 0); -- select inputs
Y: out STD_LOGIC_VECTOR (0 to 3) ); -- decoded outputs
end V2to4dec;

architecture behavior of V2to4dec is
signal Y_s: STD_LOGIC_VECTOR (0 to 3);
begin
process(EN, I, Y_s)
begin
case I is
when "00" => Y_s <= "0001";
when "01" => Y_s <= "0010";
when "10" => Y_s <= "0100";
when "11" => Y_s <= "1000";
when others => Y_s <= "0000";
end case;
if EN='1' then Y <= Y_s;
else Y <= "0000";
end if;
end process;
end behavior;

The 74x139 Dual 2-to-4 Decoder

Two independent and identical 2-to-4 decoders are contained in a single MSI part, the 74x139. The gate-level circuit diagram for this IC is shown in Figure 4(a).

Note:

1.   The outputs and the enable input of the ’139 are active-low. Most MSI decoders were originally designed with active-low outputs, since TTL inverting gates are generally faster than noninverting ones.

2.   The ’139 has extra inverters on its select inputs. Without these inverters, each select input would present three AC or DC loads instead of one, consuming much more of the fanout budget of the device that drives it.


Figure 4: The 74x139 dual 2-to-4 Decoder (a) Logic Diagram, including pin numbers for a standard 16-pin dual-in-line package (b) Traditional Logic Symbol (c) Logic Symbol for one Decoder

A logic symbol for the 74x139 is shown in Figure 4(b). All of the signal names inside the symbol outline are active-high (no “_L”), and that inversion bubbles indicate active-low inputs and outputs. Often a schematic may use a generic symbol for just one decoder, one-half of a ’139, as shown in figure 4(c). In this case, the assignment of the generic function to one half or the other of a particular ’139 package can be deferred until the schematic is completed.

Table 3: Truth Table for one-half of a 74x139 dual 2-to-4 Decoder

Table 3 is the truth table for a 74x139-type decoder. The truth tables in some manufacturers’ data books use L and H to denote the input and output signal voltage levels, so there can be no ambiguity about the electrical function of the device; a truth table written this way is sometimes called a function table.

The truth table gives the logic function in terms of the external pins of the device. A truth table for the function performed inside the symbol outline.

Some logic designers draw the symbol for 74x139s and other logic functions without inversion bubbles. Instead, they use an overbar on signal names inside the symbol outline to indicate negation. This notation is self-consistent, but it is inconsistent with our drawing standards for bubble-to-bubble logic design.

Behavioral Model

library IEEE;
use IEEE.std_logic_1164.all;

entity V74x139 is
port (EN_L: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (1 downto 0);
Y_L: out STD_LOGIC_VECTOR (0 to 3) );
end V74x139;

architecture behavior of V74x139 is
signal Y_s: STD_LOGIC_VECTOR (0 to 3);
begin
process(EN_L, A, Y_s)
begin
case A is
when "00" => Y_s <= "1110";
when "01" => Y_s <= "1101";
when "10" => Y_s <= "1011";
when "11" => Y_s <= "0111";
when others => Y_s <= "1111";
end case;
if EN_L='0' then Y <= Y_s;
else Y_L <= "1111";
end if;
end process;
end behavior;


The 74x138 3-to-8 Decoder

The 74x138 is a commercially available MSI 3-to-8 decoder whose gate-level circuit diagram and symbol are shown in Figure 5; its truth table is given in Table 4. Like the 74x139, the 74x138 has active-low outputs, and it has three enable inputs (G1, /G2A, /G2B), all of which must be asserted for the selected output to be asserted.

Table 4: Truth Table for a 74x138 3-to-8 Decoder


Figure 5: The 74x138 3-to-8 Decoder (a) Logic Diagram, including pin numbers for a standard 16-pin dual-in-line package (b) Traditional Logic Symbol

The logic function of the ’138 is straightforward—an output is asserted if and only if the decoder is enabled and the output is selected. Thus, we can easily write logic equations for an internal output signal such as Y5 in terms of the internal input signals:



However, because of the inversion bubbles, we have the following relations between internal and external signals:


Therefore, if we’re interested, we can write the following equation for the external output signal Y5_L in terms of external input signals:


Dataflow Model

library IEEE;
use IEEE.std_logic_1164.all;

entity V74x138 is
port (G1, G2A_L, G2B_L: in STD_LOGIC; -- enable inputs
A: in STD_LOGIC_VECTOR (2 downto 0); -- select inputs
Y_L: out STD_LOGIC_VECTOR (0 to 7) ); -- decoded outputs
end V74x138;

architecture dataflow of V74x138 is
signal Y_L_i: STD_LOGIC_VECTOR (0 to 7);
begin
with A select Y_L_i <=
"01111111" when "000",
"10111111" when "001",
"11011111" when "010",
"11101111" when "011",
"11110111" when "100",
"11111011" when "101",
"11111101" when "110",
"11111110" when "111",
"11111111" when others;
Y_L <= Y_L_i when (G1 and not G2A_L and not G2B_L)='1' else "11111111";
end dataflow;

Behavioral Model

architecture behavior of V3to8dec is
signal Y_s: STD_LOGIC_VECTOR (0 to 7);
begin
process(A, G1, G2A_L, G2B_L, Y_s)
begin
case A is
when "000" => Y_s <= "01111111";
when "001" => Y_s <= "10111111";
when "010" => Y_s <= "11011111";
when "011" => Y_s <= "11101111";
when "100" => Y_s <= "11110111";
when "101" => Y_s <= "11111011”;
when "110" => Y_s <= "11111101";
when "111" => Y_s <= “11111110";
when others => Y_s <= "11111111";
end case;

if (G1 and not G2A_L and not G2B_L)='1' then
Y <= Y_s;
else
Y_L <= "11111111";
end if;

end process;
end behavior;

architecture behav of V3to8dec is
begin
process (G1, G2A_L, G2B_L, A)
variable i: INTEGER range 0 to 7;
begin
Y_L <= "11111111";
if (G1 and not G2A_L and G2B_L) = '1' then
for i in 0 to 7 loop
if (i=CONV_INTEGER(A)) then Y_L(i) <= '1'; end if;
end loop;
end if;
end process;
end behav;

Structural Model

architecture structural of V3to8dec is
signal S1,S2,S3,S4,S5,S6,S7,S8: STD_LOGIC;

component inv
port (I: in STD_LOGIC;
       O: out STD_LOGIC);
end component;

component nand3
port (I0, I1, I2: in STD_LOGIC;
O: out STD_LOGIC);
end component;

component nand4
port (I0, I1, I2,I3: in STD_LOGIC;
O: out STD_LOGIC);
end component;

begin
U1: inv port map (G1,S1);
U2: nand3 port map (S1,G2A_L,G2B_L,S2);
U3: inv port map (A(2),S3);
U4: inv port map (A(1),S4);
U5: inv port map (A(0),S5);
U6: inv port map (S3,S6);
U7: inv port map (S4,S7);
U8: inv port map (S5,S8);
U9: nand4 port map (S2,S5,S4,S3,Y_L(0));
U10: nand4 port map (S2,S5,S4,S6,Y_L(1));
U11: nand4 port map (S2,S5,S7,S3,Y_L(2));
U12: nand4 port map (S2,S5,S7,S6,Y_L(3));
U13: nand4 port map (S2,S8,S4,S3,Y_L(4));
 U14: nand4 port map (S2,S8,S4,S6,Y_L(5));
U15: nand4 port map (S2,S8,S7,S3,Y_L(6));
U16: nand4 port map (S2,S8,S7,S6,Y_L(7));
end structural;

library IEEE;
use IEEE.std_logic_1164.all;

entity inv is
port (I: in STD_LOGIC;
       O: out STD_LOGIC);
end inv;

architecture dataflow of inv is
begin
O<=not I;
end dataflow;

library IEEE;
use IEEE.std_logic_1164.all;

entity nand3 is
port (I0,I1,I2: in STD_LOGIC;
       O: out STD_LOGIC);
end inv;

architecture dataflow of nand3 is
begin
O<=(I0 nand I1) nand I2;
end dataflow;

library IEEE;
use IEEE.std_logic_1164.all;

entity nand4 is
port (I0,I1,I2,I3: in STD_LOGIC;
       O: out STD_LOGIC);
end inv;

architecture dataflow of nand3 is
begin
O<=(I0 nand I1) nand (I2 nand I3);
end dataflow;

Cascading Binary Decoders

Multiple binary decoders can be used to decode larger code words. Figure 6 shows how two 3-to-8 decoders can be combined to make a 4-to-16 decoder.

The availability of both active-high and active-low enable inputs on the 74x138 makes it possible to enable one or the other directly based on the state of the most significant input bit. The top decoder (U1) is enabled when N3 is 0, and the bottom one (U2) is enabled when N3 is 1.


Figure 6: Design of a 4-to-16 Decoder using 74x138s

To handle even larger code words, binary decoders can be cascaded hierarchically. Figure 7 shows how to use half of a 74x139 to decode the two high order bits of a 5-bit code word, thereby enabling one of four 74x138s that decode the three low-order bits.

Structural Model

library IEEE;
use IEEE.std_logic_1164.all;

entity V4to16dec is
port (EN_L: in STD_LOGIC; -- enable inputs
N: in STD_LOGIC_VECTOR (3 downto 0); -- select inputs
DEC_L: out STD_LOGIC_VECTOR (0 to 15) ); -- decoded outputs
end V4to16dec;

architecture structural of V4to16dec is
component V74x138
port (G1, G2A_L, G2B_L: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (2 downto 0);
Y_L: out STD_LOGIC_VECTOR (0 to 7) );
end component;

begin
U1: V74x138 port map (‘1’,N(3),EN_L,N(0 to 2),DEC_L(0 to 7));
U2: V74x138 port map (N(3),EN_L,’0’,N(0 to 2),DEC_L(8 to 15));
end structural;

library IEEE;
use IEEE.std_logic_1164.all;

entity V74x138 is
port (G1, G2A_L, G2B_L: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (2 downto 0);
Y_L: out STD_LOGIC_VECTOR (0 to 7) );
end V74x138;

architecture behav of V3to8dec is
begin
process (G1, G2A_L, G2B_L, A)
variable i: INTEGER range 0 to 7;
begin
Y_L <= "11111111";
if (G1 and not G2A_L and G2B_L) = '1' then
for i in 0 to 7 loop
if (i=CONV_INTEGER(A)) then Y_L(i) <= '1'; end if;
end loop;
end if;
end process;
end behav;


Figure 7: Design of a 5-to-32 Decoder using 74x138s and 74x139

Structural Model

library IEEE;
use IEEE.std_logic_1164.all;

entity V5to32dec is
port (EN1,EN2_L,EN3_L: in STD_LOGIC;
N: in STD_LOGIC_VECTOR (4 downto 0);
DEC_L: out STD_LOGIC_VECTOR (0 to 31) );
end V5to32dec;

architecture structural of V4to16dec is
signal EN0x7_L,EN8x15_L,EN16x23_L,EN24x31_L: STD_LOGIC;

component V74x138
port (G1, G2A_L, G2B_L: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (2 downto 0);
Y_L: out STD_LOGIC_VECTOR (0 to 7) );
end component;

component V74x139
port (EN_L: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (1 downto 0);
Y_L: out STD_LOGIC_VECTOR (0 to 3) );
end component;

begin
U1: V74x139 port map (EN3_L, N(3), N(4), EN0x7_L, EN8x15_L, EN16x23_L, EN24x31_L);
U2: V74x138 port map (EN1, EN2_L, EN0x7_L, N(0 to 2), DEC_L(0 to 7));
U3: V74x138 port map (EN1, EN2_L, EN8x15_L, N(0 to 2), DEC_L(8 to 15));
U4: V74x138 port map (EN1, EN2_L, EN16x23_L, N(0 to 2), DEC_L(16 to 23));
U5: V74x138 port map (EN1, EN2_L, EN24x31_L, N(0 to 2), DEC_L(24 to 31));
end structural;

library IEEE;
use IEEE.std_logic_1164.all;

entity V74x138 is
port (G1, G2A_L, G2B_L: in STD_LOGIC; -- enable inputs
A: in STD_LOGIC_VECTOR (2 downto 0); -- select inputs
Y_L: out STD_LOGIC_VECTOR (0 to 7) ); -- decoded outputs
end V74x138;

architecture behav of V3to8dec is
begin
process (G1, G2A_L, G2B_L, A)
variable i: INTEGER range 0 to 7;
begin
Y_L <= "11111111";
if (G1 and not G2A_L and G2B_L) = '1' then
for i in 0 to 7 loop
if (i=CONV_INTEGER(A)) then Y_L(i) <= '1'; end if;
end loop;
end if;
end process;
end behav;

library IEEE;
use IEEE.std_logic_1164.all;

entity V74x139 is
port (EN_L: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (1 downto 0);
Y_L: out STD_LOGIC_VECTOR (0 to 3) );
end V74x139;

architecture behavior of V74x139 is
signal Y_s: STD_LOGIC_VECTOR (0 to 3);
begin
process(EN_L, A, Y_s)
begin
case A is
when "00" => Y_s <= "1110";
when "01" => Y_s <= "1101";
when "10" => Y_s <= "1011";
when "11" => Y_s <= "0111";
when others => Y_s <= "1111";
end case;
if EN_L='0' then Y <= Y_s;
else Y_L <= "1111";
end if;
end process;
end behavior;

Seven-Segment Decoders

A seven-segment display normally uses light-emitting diodes (LEDs) or liquid-crystal display (LCD) elements, is used in watches, calculators, and instruments to display decimal data. A digit is displayed by illuminating a subset of the seven line segments shown in Figure 8(a).


Figure 8: Seven segment display (a) segment identification (b) decimal digits

A seven-segment decoder has 4-bit BCD as its input code and the “seven segment code,” which is graphically depicted in Figure 8(b), as its output code.

Figure 9 and Table 5 are the logic diagram truth table and for a 74x49 seven-segment decoder. The “blanking input” BI_L is used to reset and each output of the 74x49 is a minimal product-of-sums realization for the corresponding segment, assuming “don’t-cares” for the nondecimal input combinations. The INVERT-OR-AND structure used is a fairly fast and compact structure to build in CMOS or TTL.

Most modern seven-segment display elements have decoders built into them, so that a 4-bit BCD word can be applied directly to the device. Many of the older, discrete seven-segment decoders have special high-voltage or high current outputs that are well suited for driving large, high-powered display elements.



Figure 9: The 74x49 seven-segment decoder (a) Logic Diagram, including pin numbers (b) Traditional Logic Symbol

Table 5: Truth Table for a 74x49 seven-segment decoder


Behavioral Modeling

library IEEE;
use IEEE.std_logic_1164.all;

entity V74x49 is
port (BI_L: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (3 downto 0);
Y: out STD_LOGIC_VECTOR (6 downto 0));
end V74x49;

architecture behavior of V74x49 is
signal Y_s: STD_LOGIC_VECTOR (0 to 3);
begin
process(BI_L, A, Y_s)
begin
case A is
when "0000" => Y_s <= "1111110";
when "0001" => Y_s <= "0110000";
when "0010" => Y_s <= "1101101";
when "0011" => Y_s <= "1111001";
when "0100" => Y_s <= "0110011";
when "0101" => Y_s <= "1011011";
when "0110" => Y_s <= "0011111";
when "0111" => Y_s <= "1110000";
when "1000" => Y_s <= "1111111";
when "1001" => Y_s <= "1110011";
when "1010" => Y_s <= "0001101";
when "1011" => Y_s <= "0011001";
when "1100" => Y_s <= "0100011";
when "1101" => Y_s <= "1001011";
when "1110" => Y_s <= "0001111";
when "1111" => Y_s <= "0000000";
when others => Y_s <= "0000000";
end case;
if BI_L='1' then Y <= Y_s;
else Y <= "0000000";
end if;
end process;
end behavior;


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