Unit-V
COMBINATIONAL
LOGIC DESIGN
Encoders
If the device’s output code
has fewer bits than the input code, the device is usually called an encoder.
Eg., consider a device with eight input bits representing an unsigned binary
number, and two output bits indicating whether the number is prime or divisible
by 7, then the device is called as a lucky/prime encoder.
Probably the simplest
encoder to build is a 2n-to-n or binary encoder. As shown
in Figure 1(a), it has just the opposite function as a binary decoder— its
input code is the 1-out-of-2n code and its output code is n-bit
binary. The equations for an 8-to-3 encoder with inputs I0–I7 and outputs Y0–Y2 are
The corresponding logic circuit is
shown in figure 1(b). In general, a 2n-to-n encoder can be built
from n 2n-1-input OR gates. Bit i of the input code
is connected to OR gate j if
bit j in the binary representation of i is 1.
Figure
1: Binary Encoder (a) General Structure (b) 8-to-3 Encoder
Priority Encoders
The 1-out-of-2n coded
outputs of an n-bit binary decoder are generally used to control a set
of 2n devices, where at most one device is supposed to be active at any
time. Conversely, consider a system with 2n inputs, each of which
indicates a request for service, as in Figure 2. This structure is often found
in microprocessor input/output subsystems, where the inputs might be interrupt
requests.
Figure
2: A system with 2n requestors, and a “request encoder” that
indicates which request signal is asserted at any time.
If multiple requests can be
made simultaneously, then encoder shown in
figure 1 gives undesirable results. Eg., suppose that inputs I2 and I4 of the 8-to-3 encoder are both 1; then the output is 110,
the binary encoding of 6.
Solution: Assign priority to the
input lines, so that when multiple requests are asserted, the encoding device produces
the number of the highest-priority requestor, called as a priority encoder.
Figure
3: Logic Symbol for a generic 8-input priority encoder.
The logic symbol for an 8-input
priority encoder is shown in Figure 3. Input I7 has the highest priority. Outputs A2–A0 contain the number of the highest priority
asserted input, if any. The IDLE output is asserted if no inputs are asserted.
In order to write logic equations for
the priority encoder’s outputs, we first define eight intermediate variables H0–H7, such that Hi is 1 if and only if Ii is the highest priority 1 input:
Using these signals, the equations for
the A2–A0 outputs
are similar to the ones for a simple binary encoder:
The IDLE output is 1 if no inputs are 1:
The 74x148 Priority Encoder
The 74x148 is a commercially available, MSI 8-input
priority encoder, whose logic symbol is shown in Figure 4 and its schematic is
shown in Figure 5.
Table 1: Truth Table for a
74x148 8-input priority encoder
Figure 4: Logic symbol for
the 74x148 8-input priority encoder
Figure 5: Logic diagram for the 74x148 8-input priority encoder,
including pin numbers for a standard 16-pin dual in-line package
The main difference between
this IC and the “generic” priority encoder of Figure 5 is that its inputs and
outputs are active low. It has an enable input, EI_L, that must be asserted for
any of its outputs to be asserted. The complete truth table is given in Table 1.
Instead of an IDLE output, the ’148 has a GS_L
output that is asserted
when the device is enabled and one or more of the request inputs is asserted,
called as “Group Select”. The EO_L signal is an enable output designed to be
connected to the EI_L input of another ’148 that handles lower-priority requests. /EO is asserted if EI_L is asserted but no request
input is asserted; thus, a lower-priority ’148 may be enabled.
Behavioral Modeling
library
IEEE;
use
IEEE.std_logic_1164.all;
use
IEEE.std_logic_arith.all;
entity
V74x148 is
port
(
EI_L:
in STD_LOGIC;
I_L:
in STD_LOGIC_VECTOR (7 downto 0);
A_L:
out STD_LOGIC_VECTOR (2 downto 0);
EO_L,
GS_L: out STD_LOGIC
);
end
V74x148;
architecture
V74x148p of V74x148 is
signal
EI: STD_LOGIC; --
active-high version of input
signal
I: STD_LOGIC_VECTOR (7 downto 0); --
active-high version of inputs
signal
EO, GS: STD_LOGIC; -- active-high version of
outputs
signal
A: STD_LOGIC_VECTOR (2 downto 0); -- active-high version of outputs
begin
process
(EI_L, I_L, EI, EO, GS, I, A)
variable
j: INTEGER range 7 downto 0;
begin
EI
<= not EI_L; -- convert input
I
<= not I_L; -- convert inputs
EO
<= '1'; GS <= '0'; A <= "000";
if
(EI)='0' then EO <= '0';
else
for j in 7 downto 0 loop
if
GS = '1' then null;
elsif
I(j)='1' then
GS
<= '1'; EO <= '0'; A <= CONV_STD_LOGIC_VECTOR(j,3);
end
if;
end
loop;
end
if;
EO_L
<= not EO; -- convert output
GS_L
<= not GS; -- convert output
A_L
<= not A; -- convert outputs
end
process;
end V74x148p;
Figure 6 shows how four
74x148s can be connected in this way to accept 32 request inputs and produce a
5-bit output, RA4–RA0, indicating the highest-priority requestor. Since the A2–A0 outputs of at most one ’148
will be enabled at any time, the outputs of the individual ’148s can be ORed to produce RA2–RA0.
Similarly, the individual GS_L outputs can be combined in a 4-to-2 encoder to
produce RA4 and RA3. The RGS output is asserted if any GS
output is asserted.
Structural
Model
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity V32to5en is
port (REQ_L: in STD_LOGIC_VECTOR(31 downto 0);
RGS: out STD_LOGIC;
RA: out STD_LOGIC_VECTOR(4 downto 0));
end V32to5en;
architecture structural of V32to5en is
signal GEO_L: STD_LOGIC_VECTOR(3 downto 1);
signal G0A_L, G1A_L, G2A_L, G3A_L: STD_LOGIC_VECTOR(2
downto 0);
signal GGS_L: STD_LOGIC_VECTOR(3 downto 0);
component
V74x148
port
( EI_L: in STD_LOGIC;
I_L:
in STD_LOGIC_VECTOR (7 downto 0);
A_L:
out STD_LOGIC_VECTOR (2 downto 0);
EO_L,
GS_L: out STD_LOGIC);
end component;
component V74x20
port (I0,I1,I2,I3: in STD_LOGIC;
O:
out STD_LOGIC);
end component;
component V74x00
port (I0, I1: in STD_LOGIC;
O: out STD_LOGIC);
end component;
begin
U1: V74x148 port map (‘0’, REQ_L(31 downto 24),
G3A_L(2 downto 0), GEO_L(3),GGS_L(3));
U2: V74x148 port map (GEO_L(3), REQ_L(23 downto
16), G2A_L(2 downto 0), GEO_L(2),GGS_L(2));
U3: V74x148 port map (GEO_L(2), REQ_L(15 downto
8), G1A_L(2 downto 0), GEO_L(1),GGS_L(1));
U4: V74x148 port map (GEO_L(1), REQ_L(7 downto 0),
G0A_L(2 downto 0), OPEN,GGS_L(0));
U5: nand2 port map (GGS_L(3),GGS_L(2),RA(4));
U6: nand2 port map (GGS_L(3),GGS_L(1),RA(3));
U7: nand4 port map (G3A_L(2),G2A_L(2),G1A_L(2),G0A_L(2),RA(2));
U8: nand4 port map (G3A_L(1),G2A_L(1),G1A_L(1),G0A_L(1),RA(1));
U9: nand4 port map (G3A_L(0),G2A_L(0),G1A_L(0),G0A_L(0),RA(0));
U10: nand4 port map (GGS_L(3),GGS_L(2),GGS_L(1),GGS_L(0),RGS);
end structural;
library
IEEE;
use
IEEE.std_logic_1164.all;
entity
V74x00 is
port
(I0,I1: in STD_LOGIC;
O:
out STD_LOGIC);
end
V74x00;
architecture
dataflow of V74x00 is
begin
O
<= I0 nand I1;
end
dataflow;
library
IEEE;
use
IEEE.std_logic_1164.all;
entity
V74x20 is
port
(I0,I1,I2,I3: in STD_LOGIC;
O:
out STD_LOGIC);
end
V74x20;
architecture
dataflow of V74x20 is
begin
O
<= (I0 nand I1) nand (I2 nand I3);
end
dataflow;
library
IEEE;
use
IEEE.std_logic_1164.all;
use
IEEE.std_logic_arith.all;
entity
V74x148 is
port
(
EI_L:
in STD_LOGIC;
I_L:
in STD_LOGIC_VECTOR (7 downto 0);
A_L:
out STD_LOGIC_VECTOR (2 downto 0);
EO_L,
GS_L: out STD_LOGIC
);
end
V74x148;
architecture
V74x148p of V74x148 is
signal
EI: STD_LOGIC;
signal
I: STD_LOGIC_VECTOR (7 downto 0);
signal
EO, GS: STD_LOGIC;
signal
A: STD_LOGIC_VECTOR (2 downto 0);
begin
process
(EI_L, I_L, EI, EO, GS, I, A)
variable
j: INTEGER range 7 downto 0;
begin
EI
<= not EI_L; -- convert input
I
<= not I_L; -- convert inputs
EO
<= '1'; GS <= '0'; A <= "000";
if
(EI)='0' then EO <= '0';
else
for j in 7 downto 0 loop
if
GS = '1' then null;
elsif
I(j)='1' then
GS
<= '1'; EO <= '0'; A <= CONV_STD_LOGIC_VECTOR (j,3);
end
if;
end
loop;
end
if;
EO_L
<= not EO;
GS_L
<= not GS;
A_L
<= not A;
end
process;
end V74x148p;
Figure
6: Four 74x148s cascaded to handle 32 requests
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